Multilevel Stabilizing Architecture for Overcoming Process Variation

我们设计了一组具有高故障检测和传播能力的基本单元，并通过实际的大规模集成电路设计验证了它们在鲁棒性、面积开销和电路延迟方面的优越性。此外，我们还找到了评估多重故障功能单元整体可靠性的方法，并开发了一种用异或单元代替基本单元来提高可靠性的技术。此外，我们开发了一个8way-VLIW处理器，该处理器配备了指令分解机制，这对于实现具有如此高可靠性基本单元的处理器是不可避免的，并从面积、IPC和电路延迟的角度证实了该分解机制的可行性。

We designed a group of basic cells with high capability of fault detection and propagation, and confirmed their superior effectiveness on robustness, area overhead and circuit delay through designing real LSI. Also we found the way to evaluate the overall reliability of function units that have plural faults, and developed a technique to improve the reliability by replacing basic cells with XOR cells. Moreover, we developed an 8way-VLIW processor equipped with an instruction decomposition mechanism that is inevitable for implementing processors with such high reliable basic cells, and confirmed the decomposition mechanism is feasible from the view point of area, IPC and circuit delay.