Automatic False Path Identification and Test Synthesis System Development to Avoid Overtesting

lsi设计与制造技术的进步，使得在一个芯片上实现更多的功能模块、实现高速度、低功耗成为可能。然而，由于设计中存在假路径，这也给设计带来了许多新的挑战，其中之一就是设计和测试技术。因此，在本研究中，开发了一种新的分析和测试综合系统，用于下一代lsi的低成本设计和测试，并使用该系统开发了新的测试技术，更具体地说，响应压实技术和非过度测试延迟测试方法。

The progress of design and manufacturing technology of LSIs makes it possible to realize more functional blocks into a chip with high speed and low power consumption. However it also leads to many new design challenges and one of them is the design and test technique due to the existence of false paths in the designs. Therefore in this research, a new analysis and test synthesis system was developed for the low cost design and test of next-generation LSIs, and with the use of this system novel test techniques, more specifically response compaction techniques and non-overtesting delay test methods, were developed.