FPGA design method based on self-organization maps.

放置过程是FPGA（现场可编程门阵列）设计流程中计算量很大的过程之一。虽然模拟退火算法等不确定性算法成功地解决了这一问题，但它们的速度很慢。我们已经介绍了神经网络方法，这是一种Kohonen SOM（Sefl组织特征映射）到FPGA的放置。在我们的方法中，表示网络列表的特征是很重要的。然而，仅使用连接矩阵作为输入向量在计算资源和时间方面是不够的。本文提出了一种基于shimbel指数的输入向量。我们还讨论了三种图形距离测量来提高放置质量。与使用一些基准电路进行评估的基于SA的VPR相比，我们的方法可以提高计算时间。

A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow. Although nondeterministic algorithms such as SA(Simulated Annealing) algorithm are successful in solving this problem, they are known to be slow. We have been introduced neural network approach which is a Kohonen SOM(Sefl Organizing feature Maps) to FPGA placement. In our method, it is important to represent the features of netlists. However, it is not enough to sufficient for using only connection matrix as a input vectors in terms of computational resources and time. In this paper, we proposed input vector based on a shimbel index. We also discuss three graph distance measurement to enhance placement quality. Our method can improve computational time compared with SA based VPR using some benchmark circuits in the evaluation.