Improving Hardware Verification Efficiency by Fusion of Formal Methods and Simulation

形式化方法和基于仿真的方法已被用于实际工业设计中的硬件验证。然而，如何将这两种方法联合收割机结合起来，还没有得到广泛的研究。在这项研究中，在定性验证度量方面，我们证明了我们的新方法的有效性，其中基于模拟运行的结果，一种形式化的方法被应用于提高覆盖度量。实验结果表明，对于一个有几千个门的块模块，该方法是有效的。

Formal methods and simulation-based methods have been used for hardware verification in practical industrial designs. How to combine these two methods, however, has not been studied extensively yet. In this research, in terms of qualita tive verification metrics, we show effectiveness of our new approach, in which based on the results of simulation runs, a formal method is applied for improving the coverage metrics. We also show some experimental results, in which for a block module of se veral thousands of gates, the proposed method is effective.