Research on Cirsuit Topologies for Noise Reduction in Power Electronics Circuits

电力电子电路作为节能关键技术正在广泛发展，然而，由于开关元件可能以高频重复接通/关断动作，因此产生开关噪声。 传统的降低噪声的方法是在主电路中安装噪声滤波器、缓冲元件等，这导致了体积或重量的增加以及成本的上升，并且这些方法花费了大量的时间。 本文介绍了一种降低三相逆变电路半导体开关寄生电容和电机内部寄生电容引起的共模噪声电流的方法，以及一种图腾柱型无桥功率因数校正变换器的降噪方法。

Power electronic circuits are widely expanding as energy-saving key technologies, however, a switching noise is generated because a switching element may repeat an on/off action at high frequency. Conventional methods to reduce a noise are post-installed noise filters, snubber elements, etc. in the main circuit, which lead to the increase in size or weight and the cost rise, and the methods had taken great time to it. This research is to reduce noise by means of the new circuit topology in a power electronics main circuit. The method of reducing the common-mode-noise current due to the parasitic capacitance of the semiconductor switch of a three phase inverter circuit and the internal parasitic capacitance in a motor and the noise reduction method in a totem pole type bridgeless power factor correction converter are described.