A Study of a Tile-based NoC System using IPs and its Design

片上网络(Network on Chip，NoC)是实现超大规模高性能片上系统的一种很有前途的解决方案。为了提高片上网络的设计效率，提出了一种在片上实现核的IP重用设计方法，开发了指令级可定制处理器IP的设计技术，并构建了其设计环境。讨论了面向应用的二维或三维片上网络，探索了高吞吐量、低延迟、低功耗的片上网络体系结构，开发了具有高性能或容错能力的路由算法。此外，针对片上系统和片上系统组成的板级系统的信号延迟问题，提出了几种布线算法，并对其进行了评估。

NoC(Network on Chip) is one of a promising solution to implement the ultra large scale system with high performance on a chip. For improving the design efficiency of NoC, an IP-reused design method was proposed to implement a core in each tile, where design techniques for instruction-level customizable processor IP were developed and its design environment was constructed. Application-specific NoCs of Two- or Three-dimension were also discussed, and NoC architectures for high throughput, low latency and low power were explored and routing algorithms with high performance or fault-tolerancy were developed. Besides, to solve a signal-delay problem of the board-level system composed of NoCs and SoCs(System on Chip), several routing algorithm ware proposed and evaluated.