Energy-Aware HW/SW Co-Design Method for Fine-Grained Power-Gated VLIW Processors

功率门控是众所周知的技术，以减少泄漏能量急剧，但它遭受的性能损失。本研究针对细粒度功率闸控超长指令字处理器，提出一种漏能感知的软硬件协同设计方法。VLIW处理器具有多个指令槽，每个功能单元都需要电源门控。本研究提出两种方法：能量感知的指令调度方法和架构探索方法。能量感知的指令调度方法考虑到功率门控效应来优化指令调度。体系结构探索方法试图找到帕累托最优的体系结构候选，特别关注功能单元的数量和指令分配。实验结果表明了该方法的有效性。

Power gating is well-known technique to reduce the leakage energy drastically, but it suffers from performance penalty. This research proposes leakage energy aware HW/SW co-design method for fine-grained power gated VLIW processors. VLIW processors have multiple instruction slots, and power gating is supposed to be applied to each functional units. This research proposes two methods: energy-aware instruction scheduling method and architecture exploration method. Energy-aware instruction scheduling method optimizes the instruction scheduling taking into account power gating effects. Architecture exploration method tries to find Pareto optimal architecture candidates, and especially focuses on the number of functional unit and instruction assignment. Experimental results show the efficiency of proposed methods.