A High-Performance High-Reliable Architecture for Better Energy Efficiency and Wear-out Toleration

为了容忍日益增加的电子误差，微处理器的传统方法是使用双模或三模冗余来实现高可靠的执行，这并不能显示出良好的能效。本研究以低功耗高性能容错为目标，开展了以下几个方面的工作：1.融合了时间和空间冗余：2.基于非TMR的永久故障定位方案；(3)支持NBTI效应的体系结构方法。本研究成果已发表在7篇期刊论文和9篇国际学术会议论文上，并有引荐人。

To tolerate the increasing electronic error, the traditional way in microprocessor is to use dual or triple modular redundancy for high-dependable execution, which does not show good energy efficiency. In this research, targeting at a low-power high-performance fault toleration, the following points have been carried out: 1. A fusion of temporal and spatial redundancy: 2. A non-TMR based scheme to locate the permanent failure; (3) Architectural method to aid NBTI effects. The results of this research have been published in 7 journal papers and 9 international conference papers with referee.