Hard-Middleware: Facilitating Reliable Machine Learning Deployment for Automotive Applications

随着晶体管比例继续推动更高的性能和能效，电子设备对大气辐射的敏感性受到更大的关注。这种辐射可能会导致设备内部出现故障。系统的可靠性越来越受到人们的考虑，特别是对于自动驾驶等安全关键应用。这些安全关键型应用，特别是在汽车领域，通常以机器学习任务为特色，例如物体检测。这类应用程序的性能和可靠性要求是不同的，并且经常随时间变化。通常，通过将通用硬件(软件)转换为定制电路(硬件)来加速应用程序。与传统的基于软件的方法相比，这可以提供巨大的速度提升。在汽车行业日益受到关注的定制硬件平台之一是现场可编程门阵列(现场可编程门阵列)。这种类型的平台允许用户利用定制硬件的优势，而不会产生生产定制硅的大量非经常性工程成本。辐射可能会在现场可编程门阵列上造成许多问题。TID(总电离剂量)是导致电路级损坏的高能粒子，使用抗辐射设备已大大减少了TID(总电离剂量)等影响。然而，SEUS(单事件扰乱)的影响必须使用SEU缓解技术来处理。SEU是导致存储单元逻辑状态反转的高能粒子。我们建议创建一个虚拟硬件或覆盖，称为“硬件中间件”，作为用户应用程序和它将在其上执行的FPGA平台之间的中介。而不是直接编程的现场可编程门阵列，我们提出了这种虚拟硬件的目标。然后，将在物理硬件上实现覆盖。这将允许体系结构动态适应不断变化的应用程序要求和环境条件。然后，可以在不影响应用程序设计的情况下平衡性能和效率与可靠性。然后，用户可以指定覆盖网络随后将提供的服务质量。对于给定的应用，可靠性要求可以单独和透明地考虑。覆盖层将利用现有的强化方法来实现给定应用程序所需的可靠性级别。CGRA(粗粒度可重配置阵列)是通用处理器和定制电路之间的中间地带。与现场可编程门阵列的位级运算相比，硬件被组织成可执行字级运算的处理元件阵列。由于计算单元的粗粒度特性，CGRA的配置速度可以比FPGA快得多。我们将使用CGRA作为我们的虚拟硬件。用户将该体系结构定位在较高级别，而体系结构本身将映射到较低级别的FPGA。CGRA和FPGA之间将提供保护机制，这意味着用户只需要将他们的应用映射到CGRA。使用这种类型的体系结构使我们能够利用关注CGRA开发的现有研究，并将我们的努力集中在提供用户不需要详细考虑的自动性能-可靠性权衡上。在汽车行业部署现代机器学习应用程序将有助于自动驾驶系统能力的一步改变。虽然我们的研究主要集中在汽车领域，但在硬件越来越不可靠的情况下，这将对继续进行高可靠性计算有更广泛的好处。

As transistor scaling continues to push for greater performance and energy efficiency, the susceptibility of electronic devices to atmospheric radiation is of greater concern. Such radiation can cause failure within a device. The reliability of a system is of increasing consideration, especially for safety-critical applications such as autonomous driving. These safety-critical applications, particularly in the automotive sector, often feature machine learning tasks, such as object detection. Performance and reliability requirements of such applications are varied and often change over time. Normally, applications are accelerated through the translation of general-purpose hardware (software) to bespoke circuitry (hardware). This can provide huge speed-ups over conventional software-based approaches. One such class of platforms for custom hardware that is of growing interest in the automotive sector are FPGAs (Field-Programmable Gate Arrays). This type of platform allows users to exploit the benefits of custom hardware without the large non-recurring engineering cost of producing custom silicon.Radiation can cause numerous problems on FPGAs. Effects such as TID (Total Ionising Dose), high energy particles that causes circuit-level damage, have been vastly reduced using radiation-hardened devices. However, the effects of SEUs (Single Event Upsets), high-energy particles that cause the logical state of a memory cell to flip, must be handled using SEU mitigation techniques.We propose the creation of a virtual hardware, or overlay, dubbed "Hard-Middleware" to act as an intermediary between the user's application and the FPGA platform it will execute on. Rather than programming the FPGA directly, we propose the targeting of this virtual hardware. The overlay will then be realised on physical hardware. This will allow the architecture to adapt dynamically to changing application requirements and environmental conditions. Performance and efficiency can then be balanced with reliability without affecting the design of the application. The user can then specify qualities of service that the overlay will then deliver. For a given application, the reliability requirements can be considered separately and transparently. The overlay will utilise existing hardening methodologies to realise the required level of reliability for a given application. CGRAs (Coarse Grain Reconfigurable Arrays) are a middle ground between general-purpose processors and bespoke custom circuitry. Hardware is organised into an array of processing elements that can perform word-level operations, compared with FPGAs bit-level operations. Due to the coarse-grained nature of the compute units, a CGRA can be configured much faster than an FPGA. We will use a CGRA as our virtual hardware. The user will target this architecture at a higher level, while the architecture itself will be mapped to an FPGA at a low-level. Protection mechanisms will be provided between the CGRA and the FPGA, meaning that the user need only map their application to the CGRA. Using this type of architecture allows us to draw on the pre-existing research that has focused on the development of CGRAs and focus our efforts on providing an automatic performance-reliability trade-off that the user need not consider in detail. Enabling the deployment of modern machine learning applications in the automotive sector will facilitate a step change in the capability of autonomous driving systems. Although our research focuses on the automotive sector, it will be of wider benefit to the continuation of high-reliability computation in the face of increasingly unreliable hardware.