A comparison of AArch64 and RISC-V through accurate simulation

该项目属于EPSRC架构和操作系统研究领域。ARM的AArch64指令集架构(ISA)目前正成为高性能计算(HPC)和云领域x86系统的关键替代方案。最引人注目的是它最近在A64FX芯片上的使用，该芯片用于Fugaku，到2022年6月为止，Fugaku是世界上最强大的超级计算机[1]。作为精简指令集计算机(RISC)的天然竞争对手是RISC-V。最近在加州大学伯克利分校开发了这个开源ISA，由于它简单、免费使用和开放修改，因此开始在现实世界的应用程序中使用，所有这些功能都不是ARM的指令集提供的。谷歌(Google)和亚马逊(Amazon)等大型科技公司现在正转向使用自己的内部硅片，用于其云数据中心。在设计这些系统时，首先也是最基本的决定之一是ISA，因为这会影响芯片微体系结构的其他所有部分。但目前，没有比较多个指令集的客观数据，这意味着这些决定必须使用更主观的衡量标准，而不是确凿的证据。我研究的最初目标之一是获得客观数据，以便对AArch64和RISC-V进行公平比较。首先，我将对运行许多常用编译器所针对的一系列HPC代码所需的指令数进行实验。接下来，我将确定指令计数的这种差异是否会影响在现代、高性能、无序的超标量处理器上运行这些代码所需的时间。为此，我将帮助开发SimEng[2]；这是一个快速、准确、易于修改的开源处理器模拟器，目前正在由布里斯托尔大学HPC研究小组开发。到目前为止，具有所有这些特性的模拟器还没有公开上市。目前，在该领域中，有两种方法可用于精确的处理器模拟：内部模拟器，其不能提供容易重现的结果；或Gem5[3]，其通常难以修改且模拟时间较慢。SimEng解决了这些问题，允许轻松获得和可重现的结果。我的目标是使用相同的微体系结构后端为每个ISA设置不同的前端来设置模拟。通过此模拟运行编译到每个ISA的许多不同代码，将在现代最先进的处理器中实现时，对两个ISA进行公平的比较。如果没有SimEng，这项实验将很难进行，但将为科技公司提供宝贵的数据，为他们关于下一代云和HPC系统的决策提供信息。这项工作的部分资金来自华为，他们正在帮助支持SimEng.1中的rv32。[Online]https://www.top500.org/lists/top500/2021/11/2.[Online]https://github.com/UoB-HPC/SimEng3.[在线]https://www.gem5.org/

This project falls under the EPSRC architectures and operating systems research area.Arm's AArch64 instruction set architecture (ISA) is currently establishing itself as a key alternative to x86 systems in the high performance computing (HPC) and cloud fields. This is most notably seen by its recent use in the A64FX chip, used within Fugaku, the most powerful supercomputer in the world up until June 2022 [1]. As a reduced instruction set computer (RISC), a natural competitor is RISC-V. Having been recently developed at UC Berkley, this open source ISA is starting to gain traction for use in real world applications due to it being simple, free to use, and open to modification, all features not provided by Arm's instruction set. Large technology companies such as Google and Amazon are now moving towards the use of their own, in-house silicon for use in their cloud data centres. One of the first and most fundamental decisions to be made when designing these systems is the ISA, as this can affect every other part of a chip's microarchitecture. But currently, there is no objective data comparing multiple instruction sets, meaning these decisions must be made using more subjective metrics rather than hard evidence. One of the initial aims of my research is to gain objective data allowing for a fair comparison of AArch64 and RISC-V. Firstly, I will conduct experiments into the instruction counts needed to run a range of HPC codes targeted by many commonly used compilers. As a follow up to this, I will determine if this difference in instruction count effects the time taken to run these codes on modern, high performance, out of order, superscalar processors. To do this, I will help develop SimEng [2]; a fast, accurate, easily modifiable, open source processor simulator currently in development by the University of Bristol HPC research group. A simulator with all of these qualities has, up until now, not been openly available. Currently, within the field, there are two alternatives for accurate processor simulation: in-house simulators, which do not provide easily reproducible results; or Gem5 [3], which is often hard to modify and has slow simulation times. SimEng addresses these issues, allowing for easily gained and reproducible results. My aim is to set up a simulation using the same microarchitectural backend with different front ends for each respective ISA. Running many different codes compiled to each ISA through this simulation will provide a fair comparison of the two ISAs when implemented in modern state-of-the-art processors. An experiment that, without SimEng, would have been very difficult to conduct but will provide invaluable data for tech companies informing their decisions about the next generation of cloud and HPC systems.This work is partially funded by Huawei, who are helping to support rv32 within SimEng.1. [online] https://www.top500.org/lists/top500/2021/11/2. [online] https://github.com/UoB-HPC/SimEng3. [online] https://www.gem5.org/