SElf-timed DATapath synthEsis (SEDATE)

在深亚微米技术中设计芯片变得越来越困难。在制造工艺参数的变化意味着预先确定一个安全的工作时钟率往往是过于谨慎。自定时电路消除了全局控制时钟，而采用自定时电路，并根据有效数据的可用性进行操作。在过去，这种电路的设计是困难的，但在过去的10年里，在自动合成自定时电路的工具方面取得了很大的进步。然而，这些自动工具最适合于控制电路或低性能系统。这项工作将开发用于自动合成自定时数据路径的新算法，并将这些工具嵌入到一个框架中，使设计人员能够从各种自定时实现设计风格中进行选择。设计师将能够从一系列实现中进行选择，从那些对组件延迟完全不敏感的实现，到那些使用基于实际布局参数的相对时序约束进行积极计时的实现。通过将面向测试的设计技术和相关的时间限制合并到数据路径体系结构中，将充分利用它们。拟议研究的重点将是自动生成自定时数据路径结构，如针对标准单元库的管道和低延迟组合块。

Designing chips in deep-sub micron technologies is becoming increasing difficult. Parameter variations in fabrication processes mean that pre-determining a safe operating clock-rate is often over cautious. Self-timed circuits eliminate the global controlling clock in favour of circuits which are self-timed and which operate in response the availability of valid data. In the past, the design of such circuits has been difficult but in the last 10 years, great advances have been made in tools for the automatic synthesis of self-timed circuits. However, these automatic tools are best suited to control circuits or to low performance systems.This work will develop novel algorithms for the automatic synthesis of self-timed datapaths and will embed these tools in a framework that will allow a designer to choose from a variety of self-timed implementation design styles. A designer will be able choose from a range of implementations / from those that are completely insensitive to delays within components to those which are aggressively-timed using relative timing constraints based on actual layout parameters. Design-for-test techniques and relative timing constraints will be fully exploited by incorporating them into the datapath architecture. The focus of the proposed research will be the automated generation of self-timed datapath structures such as pipelines and low-latency combinational blocks targeted at standard cell libraries.