Hardware-accelerated prototyping, characterization and optimization of multiple-antenna communication transmitters and receivers

拟议的研究计划的主要目标是开发，扩展和演示使用现场可编程门阵列（FPGA），大大加快无线通信系统的仿真方法。 多天线无线通信系统的设计者面临着一个快速升级的挑战，其中所提出的发射机和接收机的设计必须在广泛的可能的设计配置和无线信道条件下进行验证和优化。 每个候选设计的性能必须使用长时间运行的仿真进行验证，仿真中使用的数据是通过真实但复杂的无线信道模型进行通信的伪随机生成的。 为了确保统计上有意义的位和符号错误率（BER和SER）的测量，仿真的通信系统必须处理大量的传输数据位。 这种情况由于使用强大的纠错码（例如Turbo码）而变得更糟，这进一步降低了相同信道条件下的有效BER和SER，因此延长了所需的仿真。 因此，即使在最快的计算机工作站上，传统的基于软件的模拟也很容易花费数天甚至数周的时间。

The main objective of the proposed research programme is to develop, extend and demonstrate a methodology for using field-programmable gate arrays (FPGAs) to greatly accelerate the simulation of wireless communication systems. The designers of multiple-antenna wireless communication systems face a rapidly escalating challenge where the designs of proposed transmitters and receivers must be verified and optimized over a wide range of posssible design configurations and wireless channel conditions. The performance of each candidate design must be verified using long-running simulations with pseudorandomly generated data communicated over realistic but complex models of the wireless channel. To ensure statistically meaningful bit and and symbol error rate (BER and SER) measurements, the simulated communication systems must process an extremely large number of transmitted data bits. This situation is made worse by the use of powerful error correcting codes, such as Turbo codes, which further reduce the effective BER and SER for the same channel conditions and hence lengthen the required simulations. Consequently conventional software-based simulations can easily take many days and even weeks of time on even the fastest computer workstations.