Hybrid approaches for functional verification of microelectronics systems

今天的数字电路可能包含多达数亿个晶体管。人们认识到，功能验证仍然是设计过程的主要瓶颈，占其总成本的70%。通过模拟进行功能验证是一种通过派生功能测试（测试台驱动程序）来发现错误的方法，同时尝试达到设计的功能覆盖目标。由于通过测试平台驱动程序对设计的可控性有限，因此使用仿真来发现极端情况下的错误通常效率低下。 编写一个有针对性的测试来练习特定的行为可能是具有挑战性和耗时的。等待约束随机模拟来执行相同的行为也可能需要很长时间，并且不能保证真正执行了极端情况。相比之下，一个正式的验证工具可以非常成功地找到困难的错误。然而，这些工具是复杂的，它们需要大量的资源（CPU时间和内存），并且它们通常需要专业的专家，这限制了它们在设计流程中的集成。最近，新的形式化和基于仿真的技术已经发展起来，以加强功能验证过程。然而，设计复杂性的快速增加使得很难摆脱硅前缺陷，这些缺陷在每一代新设计中都不断增加。克服这种验证瓶颈的一种方法是将多种互补技术结合起来，使它们的组合强度上级单个技术的总和。在这项研究计划中，我们解决了混合验证工具和技术的发展，以实现更高的验证覆盖率的实际尺寸的微电子设计在一个实用的方式。我们相信，我们的方法将推进最先进的系统验证，从而提高缩短设计周期。这项研究的直接受益者将是加拿大的微电子工业。此外，这项建议将有助于为加拿大工业和学术界培训一些技术人员。

Today's digital circuits may contain up to several hundred million transistors. It is recognized that functional verification remains a major bottleneck of the design process, accouting for 70% of its overall costs. Functional verification by simulation is a way of finding bugs by deriving functional tests (testbench drivers) while attempting to reach functional coverage goals for the design. Finding corner-case bugs with simulation is often inefficient due to the limited controllability of the design through the testbench drivers. Writing a directed test to exercise a specific behavior can be challenging and time-consuming. Waiting for a constrained-random simulation to exercise the same behavior can also take a long time, with no guarantee that corner cases are really being exercised. In contrast, a formal verification tool can be very successful for finding difficult bugs. However, these tools are complex, they need huge resources (CPU time and memory), and they usually need specialized experts which limit their integration in the design flow. Recently, new formal and simulation based techniques has been developped to enhance the functional verification process. However, the rapid inreases in the design complexity makes it difficult to get rid of the presilicon bugs which have consistently increased for each new design generation. One way, to combat this verification bottlenck is to combine multiple, complementary techniques so that their combined strength is superior to the sum of the individual technques. In this research program, we address the development of hybrid verification tools and techniques to achieve the higher verification coverage of real-size microelectronics designs in a practical way. We believe that our approach will advance the state-of-the-art in systems verification, thus enhancing the shortening the design cycle. The direct beneficiary of this research will be the Canadian microelectronics industry. Furthermore, this proposal will contribute towards the training of a number of skilled personnel available to Canadian industry and academy.