CAD Tools for Multi/Many-core NoC and Heterogeneous Computing System Design

大量高性能（嵌入式）* 计算机系统基于多/众核架构，其应用范围从复杂的飞机或航天器飞行控制到 * 智能和超移动系统。随着摩尔定律所预测的设备规模的不断扩大，由于高功耗和体系结构的限制，计算机架构师不可能构建更快的单处理器系统。为了实现更高的性能，计算机 * 架构师正在将包括GPU（图形 * 处理单元）在内的许多异构内核集成到一个芯片上。计算系统设计 * 的最新发展使研究人员能够通过增加内核数量 * 来提高系统性能，同时控制功耗。这些系统中的核心数量正在急剧增加。GPU最初用于图形处理;然而，它们 * 正在用于广泛的计算和数据密集型应用程序。这种创新的使用趋势导致GPU制造商将 *GPU架构从纯SIMD修改为混合SIMT（单指令 * 多线程）。针对片上系统（SoC）的异构计算（包括 *CPU-GPU集群）在高端嵌入式应用中越来越受欢迎。* * 我们打算研究单芯片 * CPU-GPU集成和架构的最新趋势，以及与这些系统的任务映射和调度相关的挑战。在CPU-GPU系统上实现嵌入式应用的主要问题之一是GPU的高功耗。我们建议调查国家的最先进的任务调度和 * 映射技术，以尽量减少功耗。我们打算 * 设计应用程序分区和分配技术的 *CPU-GPU为基础的异构系统消耗最小的功率。还将为基于CPU-GPU的SoC开发在线任务映射和调度技术。* 我们一直在 * 研究基于片上网络（Network-on-Chip，NoC）的多核/众核SoC的协同综合方法。*片上通信架构对于优化众核系统的功耗 * 和性能起着至关重要的作用。从多核系统应用程序中提取高性能存在着一些挑战，例如通信，同步和利用并行性。我们最近的研究产生了高 * 影响的NoC路由器架构和通信感知的核心图映射技术。大多数现有的NoC设计工具要么与应用映射到规则拓扑相关，要么提供最佳NoC拓扑。我们将讨论几个额外的和重要的方面，如 * 片上网络综合，通信架构设计和验证的多/众核 * 系统。我们建议调查软件（CAD）工具，设计最佳的片上网络，考虑芯片面积，功耗和性能参数。一个新的和混合 * 优化方法将制定片上网络合成。

A significant number of high performance (embedded)*computer systems are based on multi/many-core architectures and their*applications range from sophisticated aircraft or spacecraft flight control to*smart and ultra-mobile systems. With the continued device scaling as predicted*by Moore's Law, it is not possible for the computer architects to build faster single*processor systems due to high power consumption and architectural*limitations. To achieve higher performance, computer*architects are accommodating many heterogeneous cores including GPUs (Graphics*Processing Units) on a chip. Recent developments in the computing system design*have enabled the researchers to improve system performance by increasing the number*of cores while keeping a check on the power consumption. The number of cores in these systems are rising dramatically. GPUs were originally intended for graphics processing; however, they*are being used for a wide range of computation and data-intensive applications.*Such innovative usage trend has led the GPU manufacturers to modify the*GPU architecture from purely SIMD to hybrid SIMT (Single Instruction*Multiple Threads). Heterogeneous computing involving*CPU-GPU clusters for a System-on-Chip (SoC) is getting popular for high-end embedded applications.*** *We intend to investigate latest trends in single chip*CPU-GPU integration and architectures as well as challenges related to task mapping and scheduling for these systems. One of the main problems associated with the implementation*of embedded application on CPU-GPU systems is the high-power consumption*associated with GPUs. We propose to investigate state of the art task scheduling and*mapping techniques to minimize power consumption. We intend to*design application partitioning and allocation techniques for*CPU-GPU based heterogeneous systems consuming minimal power. On-line task mapping and scheduling techniques will also be developed for CPU-GPU based SoCs.*** We have been*investigating co-synthesis approaches for NoC (Network-on-Chip) based multi/many-core SoCs.*On-chip communication architecture plays a crucial role to optimize the power*and performance of many-core systems. Several challenges exist to extract*high performance from the multi-core system applications such as communication,*synchronization and exploiting parallelism. Our recent research has produced high*impact NoC router architectures and communication-aware core-graph mapping techniques. Most of the existing NoC design tools are either related*to application mapping to a regular topology or provide an optimal NoC*topology. We will address several additional and important aspects such*as NoC synthesis, communication architecture design and verification of multi/many-core*systems. We propose to investigate software (CAD) tools to design optimal NoCs by considering chip area, power and performance parameters. A novel and hybrid*optimization methodology will be formulated for NoC synthesis.