Development of Energy-Efficient High-Resolution Analog-to-Digital Data Converters for Power-Constrained Applications

高效节能的高分辨率模数转换器（adc）对于广泛的新兴应用至关重要，包括用于环境监测和物联网的自主传感器、用于24/7患者健康监测的便携式医疗设备、用于检测微尺度生物医学信号的微型植入式医疗设备、用于结构监测的嵌入式传感器、机器监测和先进制造，等等。在这些应用中，模数转换器需要在低电源电压下工作，每个转换步骤的功率效率为几飞焦耳，分辨率超过12位。连续逼近寄存器（SAR）模数转换器出现于20世纪50年代，并于20世纪70年代在互补金属氧化物半导体（CMOS）中首次亮相，以低功耗，出色的技术兼容性，宽范围的转换率和良好的分辨率将自己与流水线和δ -sigma adc区分开来，是这些应用的理想候选者。该研究项目将建立在申请人在混合模式信号处理方面的先前研究和专业知识的基础上，并为功率受限的应用开发低功耗高分辨率SAR adc。研究将集中在开发新的低功耗技术，以最大限度地减少SAR adc的功耗，新的电路拓扑和技术，以最大限度地减少比较器的噪声，偏移和亚稳定性的影响，新的节能算法及其节能实现，以最大限度地减少电容式数字-时间转换器中电容失配的影响。以及混合SAR adc，在SAR adc的设计中利用基于时间的信号处理，从而在不牺牲性能的情况下利用技术缩放的优点实现最小的功耗和硅消耗。

Energy-efficient high-resolution analog-to-digital converters (ADCs) are essential for a broad range of emerging applications including autonomous sensors for environmental monitoring and internet-of-things, portable medical devices for 24/7 patient health monitoring, miniaturized implantable medical devices for detecting micro-scale biomedical signals, embedded sensors for structure monitoring, machine monitoring, and advanced manufacturing, to name a few. Analog-to-digital converters operated with a low supply voltage with the power efficiency of a few femto joules per conversion step and a resolution exceeding 12 bits are required in these applications. Successive approximation register (SAR) analog-to-digital converters emerged in 1950s and debuted in complementary metal-oxide-semiconductor (CMOS) in 1970s distinguish themselves from pipelined and delta-sigma ADCs with low power consumption, excellent technology compatibility, a wide range of conversion rate, and a good resolution, and are ideal candidates for these applications. This research project will build upon the prior research and expertise of the applicant in mixed-mode signal processing and develop low-power high-resolution SAR ADCs for power-constrained applications. Research will be focused on the development of new low-power techniques to minimize the power consumption of SAR ADCs, new circuit topologies and techniques to minimize the impact of the noise, offset, and meta-stability of comparators, new energy-efficient algorithms and their energy-efficient realization to minimize the impact of capacitor mismatch in capacitive digital-to-time converters, and hybrid SAR ADCs that make use of time-based signal processing in design of SAR ADCs so as to utilize the merits of technology scaling to achieve minimum power and silicon consumption without sacrificing performance.