Effect of Grain Boundary Protrusion on Electrical Performance of Low Temperature Polycrystalline Silicon Thin Film Transistors
Effect of Grain Boundary Protrusion on Electrical Performance of Low Temperature Polycrystalline Silicon Thin Film Transistors
复制标题
晶界凸起对低温多晶硅薄膜晶体管电性能的影响
DOI：
10.1109/jeds.2019.2911088
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发表时间：
2019
影响因子：
2.3
通讯作者：
Jin Jang
中科院分区：
文献类型：
--
作者：
M. Billah;Abu Bakar Siddik;Jung Bae Kim;Lai Zhao;Soo;D. Yim;Jin Jang
研究了晶界突出对低温多晶硅薄膜晶体管电学性能的影响。原子力显微镜和透射电镜图像分析表明，晶粒尺寸为~350 nm，突出高度为~35 nm。采用计算机辅助设计技术，对多晶硅和GB两种不同态密度的转移和输出特性进行了拟合。从二维轮廓图中，与颗粒（<inline-formula> < text -math notation="LaTeX">${\sim}5\乘10^{16}\，\,{\ mathm {cm}}^{-3}$ </ text -math notation="LaTeX">${\sim}3\乘10^{18}\，\,{\ mathm {cm}}^{-3}$ </ text -math></inline-formula>）相比，GB突出部位的孔浓度显著降低（<inline-formula> < text -math notation="LaTeX">${\sim}5\乘10^{18}\，\,{\ mathm {cm}}）。在GB处的捕获浓度要高得多，这导致迁移率降低。
We studied the impact of grain boundary (GB) protrusion on the electrical properties of low temperature polycrystalline silicon thin film transistors. The analysis of atomic force microscopy and transmission electron microscopy images indicate the grain size of ~350 nm and a protrusion height of ~35 nm. The transfer and output characteristics are well fitted by technology computer-aided design using two different density of states for poly-Si grain and GB, respectively. From 2-D contour mapping, a drastic reduction of hole concentration (<inline-formula> <tex-math notation="LaTeX">${\sim }5\times 10^{16}\,\,{\mathrm{cm}}^{-3}$ </tex-math></inline-formula>) at GB protrusion site was obtained as compared to the grain (<inline-formula> <tex-math notation="LaTeX">${\sim }3\times 10^{18}\,\,{\mathrm{cm}}^{-3} $ </tex-math></inline-formula>). Trapping concentration at GB is much higher, which leads to the reduction in the mobility.
影响因子：
4.9
作者：
SAMESHIMA, T;USUI, S;SEKIYA, M
通讯作者：
SEKIYA, M