CMOS compatible manufacturing of a hybrid SET-FET circuit
CMOS compatible manufacturing of a hybrid SET-FET circuit
复制标题
混合 SET-FET 电路的 CMOS 兼容制造
DOI：
10.1088/1361-6641/ac9f61
复制
发表时间：
2022
影响因子：
1.9
通讯作者：
F. Pérez
中科院分区：
文献类型：
--
作者：
A. del Moral;E. Amat;H. Engelmann;M. Pourteau;G. Rademaker;D. Quirion;N. Torres;M. Rommel;K. Heinig;J. von Borany;R. Tiron;J. Bausells;F. Pérez
本研究分析了互补金属氧化物半导体（CMOS）兼容制造的混合单电子晶体管场效应晶体管（SET-FET）电路的可行性。在室温下工作的SET的基本元素是垂直纳米柱（NP）与嵌入的硅纳米点产生的离子束照射。通过结构表征验证了从NP到接触SET的整合过程。然后，平面FET与垂直SET集成的单片制造，并证明其与标准CMOS工艺的兼容性。这项工作包括工艺优化、支柱完整性验证、电气特性和考虑寄生效应的模拟。FET制造工艺适于满足预制NP的要求。总体而言，这项工作奠定了基础，实现混合SET-FET电路在室温下工作。
This study analyzes feasibility of complementary metal–oxide–semiconductor (CMOS)-compatible manufacturing of a hybrid single electron transistor–field effect transistor (SET-FET) circuit. The fundamental element towards an operating SET at room temperature is a vertical nanopillar (NP) with embedded Si nanodot generated by ion-beam irradiation. The integration process from NPs to contacted SETs is validated by structural characterization. Then, the monolithic fabrication of planar FETs integrated with vertical SETs is presented, and its compatibility with standard CMOS technology is demonstrated. The work includes process optimization, pillar integrity validation, electrical characterization and simulations taking into account parasitic effects. The FET fabrication process is adapted to meet the requirements of the pre-fabricated NPs. Overall, this work establishes the groundwork for the realization of a hybrid SET-FET circuit operating at room temperature.
影响因子：
2.1
作者：
Ponon, Nikhil K.;Appleby, Daniel J. R.;O'Neill, Anthony
通讯作者：
O'Neill, Anthony