System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV
System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV
复制标题
硅片系统架构及其在 1080HDTV 的 H.264/AVC 运动估计中的应用
DOI：
10.1109/isscc.2006.1696226
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
Kenji Yoshida
中科院分区：
文献类型：
--
作者：
K. Kumagai;Changqi Yang;H. Izumino;Nobuyuki Narita;Keisuke Shinjo;Shin;Y. Nakaoka;Tomohiro Kawamura;Hideo Komabashiri;Tsukasa Minato;Atsushi Ambo;Takamasa Suzuki;Zhenyu Liu;Yang Song;S. Goto;T. Ikenaga;Yoshihiro Mabuchi;Kenji Yoshida
硅系统（SiS）是一种多芯片架构，以低功耗实现逻辑和存储器之间的宽带宽通信。介绍了SiS在H.264/AVC运动估计中的应用。 DRAM集成了23.1 Gb/s的带宽和1.6pJ/b的数据传输效率，实现了263.1GB/s的实时1080HDTV处理。作者提出了一种具有 1024b 芯片间总线的硅内系统架构，可在逻辑和存储器之间提供高带宽低功耗连接。高度并行架构还允许低频 (25MHz) 操作，同时实现 1080HDTV 的实时运动估计。该解决方案以 190mW 的功率水平实现了运动估计所需的 23.1 Gb/s 带宽和相关处理
System-in-silicon (SiS) is a multi-chip architecture to realize wide bandwidth communication between logic and memory with low power. The application of SiS to H.264/AVC motion estimation is presented. DRAM is integrated with 23.1 Gb/s bandwidth and 1.6pJ/b data transfer efficiency, realizing real-time 1080HDTV processing with 263.1GB/s. The authors present a system-in-silicon architecture with 1024b inter-chip bus to provide high-bandwidth low-power connectivity between logic and memory. The highly parallel architecture also allows low frequency (25MHz) operation while achieving real-time motion estimation for 1080HDTV. The solution achieves the required 23.1 Gb/s bandwidth and associated processing for motion estimation at a power level of 190mW
具有发射功率控制方案的 195Gb/s 1.2W 3D 堆叠感应片间无线超级连接
DOI：
--
发表时间：
2004
期刊：
IEEE International Solid-State Circuits Conference (ISSCC' 05) Dig. Tech. Papers
影响因子：
--
作者：
R. Ono;K. Takezawa;Y. Yamashita;T. Oda;N.Miura 他
通讯作者：
N.Miura 他