Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration
复制标题
用于低功耗 3D 系统集成的电感耦合芯片间链路失准容差的建模和实验验证
DOI：
10.1109/tvlsi.2009.2020724
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发表时间：
2010
影响因子：
2.8
通讯作者：
T. Kuroda
中科院分区：
文献类型：
--
作者：
K. Niitsu;Y. Kohama;Y. Sugimori;Kazutaka Kasuga;K. Osada;N. Irie;H. Ishikuro;T. Kuroda
首次提出了三维系统集成中电感耦合芯片间链路失调容限的建模和实验验证方法。堆叠芯片之间的未对准降低了片上电感器的耦合系数，并增加了发射机功率。我们提出了一个模型，它估计增加发射机功率考虑错位作为一个额外的通信距离。提出的模型进行了验证，电磁仿真和测量使用65纳米CMOS工艺制造的测试芯片。所提出的模型计算的结果与测量结果吻合良好。测量结果表明，电感耦合环节的失调容限很高，一般情况下可以忽略。
Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors and increases transmitter power. We proposed a modeling which estimates the increase in transmitter power by considering misalignment as an additional communication distance. Proposed model was verified by electromagnetic simulations and by measurements using testchips fabricated in 65-nm CMOS technology. The results calculated by the proposed modeling match well with measurement results. Measurement results show that misalignment tolerance of inductive-coupling link is well high and can be ignored in common conditions.
具有数字控制精确脉冲整形功能的 0.14pJ/b 电感耦合收发器
DOI：
--
发表时间：
2008
期刊：
IEEE Journal of Solid-State Circuits(JSSC) 43
影响因子：
--
作者：
N. Miura;H. Ishikuro;K. Niitsu;T. Sakurai;and T. Kuroda
通讯作者：
and T. Kuroda
影响因子：
5.4
作者：
N. Miura;D. Mizoguchi;T. Sakurai;T. Kuroda
通讯作者：
N. Miura;D. Mizoguchi;T. Sakurai;T. Kuroda