A Power Modeling and Estimation Framework for VLIW-based Embedded Systems
A Power Modeling and Estimation Framework for VLIW-based Embedded Systems
复制标题
基于 VLIW 的嵌入式系统的功耗建模和估计框架
DOI：
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
R. Zafalon
中科院分区：
文献类型：
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作者：
L. Benini;D. Bruni;M. Chinosi;C. Silvano;V. Zaccaria;R. Zafalon
提出了一种对嵌入式超长指令字(VLIW)体系结构进行系统级功耗建模和估算的框架。针对系统的主要组成部分，即内核、寄存器堆、指令和数据缓存，建立了POWER宏模型。这些模型已经集成在动态功率估计引擎的层次结构中，处于几个抽象级别。主要目标是定义一个系统级仿真框架(I)以动态分析软件执行期间的功率行为，以及(Ii)提供由于系统的单个组件而引起的功率贡献的细分。所提出的方法已应用于一个工业案例研究：LX系列可扩展嵌入式VLIW处理器，专为多媒体和信号处理应用而设计。针对嵌入式应用程序的一组多媒体基准测试，对所提出的方法进行了广泛的验证。实验结果表明，相对于RTL引擎，指令级估计引擎的平均准确率为5%，平均加速4个数量级
In this paper, a framework for modeling and estimating the system-level power consumption for embedded VLIW (Very Long Instruction Word) architectures is proposed. Power macro-models have been developed for the main components of the system: namely the core, the register file, the instruction and data caches. The models have been integrated within a hierarchy of dynamic power estimation engines, at several abstraction levels. The main goal is to define a system-level simulation framework (i) to profile dynamically the power behavior during software execution and (ii) to provide a break-out of the power contributions due to the single components of the system. The proposed methodology has been applied to an industrial case study: the Lx family of scalable embedded VLIW processors, designed for multimedia and signal processing applications. Extensive validation of the proposed methodology has been carried out over a set of multimedia benchmarks for embedded applications. The experimental results have demonstrated an average accuracy of 5% of the instruction-level estimation engine with respect to the RTL engine, with an average speed-up of four orders of
DOI：
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发表时间：
2023
期刊：
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影响因子：
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作者：
D. Brooks;V. Tiwari;Intel Margaret Martonosi
通讯作者：
D. Brooks;V. Tiwari;Intel Margaret Martonosi