An Adaptive STDP Learning Rule for Neuromorphic Systems.
An Adaptive STDP Learning Rule for Neuromorphic Systems.
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DOI：
10.3389/fnins.2021.741116
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发表时间：
2021
影响因子：
4.3
通讯作者：
Kohno T
中科院分区：
文献类型：
--
作者：
Gautam A;Kohno T
神经形态计算开发超低功耗智能设备的前景在于它能够在突触电路中定位信息处理和记忆存储，就像大脑中的突触一样。使用高分辨率突触建模并配备局部无监督学习规则（例如尖峰时间依赖性可塑性（STDP））的尖峰神经网络在模式检测和图像分类等任务中显示出了有希望的结果。然而，设计和实现传统的多位 STDP 电路在电路和所需的硅面积方面都变得复杂。在这项工作中，我们介绍了一种仅使用 4 位突触实现的改进且硬件友好的 STDP 学习（称为自适应 STDP）。我们在模式识别任务中展示了这种学习规则的能力，其中神经元学习识别嵌入嘈杂的非均匀泊松尖峰中的特定尖峰模式。我们的结果表明，所提出的学习规则的性能（94％仅使用 4 位突触）与传统的 STDP 学习（96％使用 64 位浮点精度）相似。本研究中使用的模型是具有模拟体细胞和突触电路以及混合信号学习电路的 CMOS 神经形态电路的理想模型。学习电路将突触权重存储在异步更新的 4 位数字存储器中。在台积电（TSMC）250 nm CMOS工艺设计套件（PDK）的电路仿真中，单个突触的静态功耗和每个尖峰的能量（产生振幅15 pA和时间常数3 ms的突触电流）分别小于2 pW和200 fJ。学习电路的静态功耗小于135 pW，处理单个学习步骤对应的一对突触前和突触后尖峰的能量小于235 pJ。单个 4 位突触（能够配置为兴奋性、抑制性或分流抑制性）及其学习电路和数字存储器占据约 17,250 μm2 的硅面积。
The promise of neuromorphic computing to develop ultra-low-power intelligent devices lies in its ability to localize information processing and memory storage in synaptic circuits much like the synapses in the brain. Spiking neural networks modeled using high-resolution synapses and armed with local unsupervised learning rules like spike time-dependent plasticity (STDP) have shown promising results in tasks such as pattern detection and image classification. However, designing and implementing a conventional, multibit STDP circuit becomes complex both in terms of the circuitry and the required silicon area. In this work, we introduce a modified and hardware-friendly STDP learning (named adaptive STDP) implemented using just 4-bit synapses. We demonstrate the capability of this learning rule in a pattern recognition task, in which a neuron learns to recognize a specific spike pattern embedded within noisy inhomogeneous Poisson spikes. Our results demonstrate that the performance of the proposed learning rule (94% using just 4-bit synapses) is similar to the conventional STDP learning (96% using 64-bit floating-point precision). The models used in this study are ideal ones for a CMOS neuromorphic circuit with analog soma and synapse circuits and mixed-signal learning circuits. The learning circuit stores the synaptic weight in a 4-bit digital memory that is updated asynchronously. In circuit simulation with Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm CMOS process design kit (PDK), the static power consumption of a single synapse and the energy per spike (to generate a synaptic current of amplitude 15 pA and time constant 3 ms) are less than 2 pW and 200 fJ, respectively. The static power consumption of the learning circuit is less than 135 pW, and the energy to process a pair of pre- and postsynaptic spikes corresponding to a single learning step is less than 235 pJ. A single 4-bit synapse (capable of being configured as excitatory, inhibitory, or shunting inhibitory) along with its learning circuitry and digital memory occupies around 17,250 μm2 of silicon area.
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影响因子：
25
作者：
Song, S;Miller, KD;Abbott, LF
通讯作者：
Abbott, LF
DOI：
10.1016/j.aeue.2009.03.009
发表时间：
2010-01-01
影响因子：
3.2
作者：
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通讯作者：
Sirinaovakul, Boonchareon
影响因子：
--
作者：
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通讯作者：
Cauwenberghs, Gert
DOI：
10.1109/tbcas.2013.2255873
发表时间：
2014-02-01
影响因子：
5.1
作者：
Moradi, Saber;Indiveri, Giacomo
通讯作者：
Indiveri, Giacomo
影响因子：
4.3
作者：
Kohno T;Sekikawa M;Li J;Nanami T;Aihara K
通讯作者：
Aihara K