Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
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用于近似整数和浮点乘法的最小偏差乘法器
DOI：
10.1109/tcad.2018.2857262
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发表时间：
2018
影响因子：
2.9
通讯作者：
S. Parameswaran
中科院分区：
文献类型：
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作者：
Hassaan Saadat;H. Bokhari;S. Parameswaran
近似乘法器可以节省面积和功耗，以实现许多现代容错计算密集型应用程序。在本文中，我们首先提出了一种新的错误可配置的最小偏置近似整数乘法器（MBM）的设计。所提出的MBM设计是通过耦合一个独特的错误减少机制与近似的基于对数的整数乘法器。接下来，我们提出了一个优化（通过删除前导一检测和桶移位逻辑）的MBM和一类最先进的近似整数乘法器（DRUM和SSM），使它们可以有效地用于近似浮点（FP）乘法器。然后，我们提出了一组新的近似FP乘数，我们表明，这些FP乘数位于帕累托前沿的面积<italic>与</italic>误差和功率<italic>与</italic>误差的设计空间。我们综合使用台积电45纳米标准单元库的设计。结果表明，MBM整数设计在设计空间中提供了最优点，与精确版本相比，面积减少了75%，功耗减少了84%，误差偏差<0.1%。所提出的近似FP乘法器比传统的精度缩放提供更好的误差效率权衡。与IEEE-754单精度FP乘法器相比，FP设计空间可以提供高达<inline-formula><tex-math notation="LaTeX">57倍的</tex-math></inline-formula>功耗和<inline-formula><tex-math notation="LaTeX">28倍的</tex-math></inline-formula>面积改进，峰值误差小于25%，平均误差小于7%，误差偏差小于4%。我们还进行了应用级评估建议的近似整数和FP乘法器，表明我们提出的乘法器，使显着的功率和面积减少，在应用程序的输出质量的最小退化。
Approximate multipliers enable the saving of area and power for implementation of many modern error-resilient compute-intensive applications. In this paper, we first propose a novel error-configurable minimally biased approximate integer multiplier (MBM) design. The proposed MBM design is devised by coupling a unique error-reduction mechanism with an approximate log based integer multiplier. Next, we propose an optimization (by removing leading-one detection and barrel shifting logic) of the MBM and a class of state-of-the-art approximate integer multipliers (DRUM and SSM), so that they can be efficiently used in approximate floating-point (FP) multipliers. Then, we propose a set of new approximate FP multipliers and we show that these FP multipliers lie on the Pareto front on the design spaces of area <italic>versus</italic> error and power <italic>versus</italic> error. We synthesize the designs using the TSMC 45-nm standard-cell library. Results show that the MBM integer design offers optimal points in the design space, offering up to 75% area reduction and 84% power reduction with <0.1% error bias, when compared with the accurate version. The proposed approximate FP multipliers offer better error-efficiency tradeoffs than traditional precision scaling. The FP design space can offer up to <inline-formula> <tex-math notation="LaTeX">$57 \times $ </tex-math></inline-formula> power and <inline-formula> <tex-math notation="LaTeX">$28 \times $ </tex-math></inline-formula> area improvement for less than 25% peak error, 7% mean error, and 4% error bias, when compared with the IEEE-754 single-precision FP multiplier. We also perform application-level evaluations of the proposed approximate integer and FP multipliers, showing that our proposed multipliers enable significant power and area reduction with minimal degradation in applications’ output quality.
DOI：
10.1145/2966986.2967005
发表时间：
2016-11
期刊：
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
影响因子：
--
作者：
Semeen Rehman;Walaa El-Harouni;M. Shafique;Akash Kumar;J. Henkel
通讯作者：
Semeen Rehman;Walaa El-Harouni;M. Shafique;Akash Kumar;J. Henkel