DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool
DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool
复制标题
DRAMSpec：高级 DRAM 时序、功耗和面积探索工具
DOI：
10.1007/s10766-016-0473-y
复制
发表时间：
2016
影响因子：
1.5
通讯作者：
N. Wehn
中科院分区：
文献类型：
--
作者：
C. Weis;A. Mutaal;O. Naji;M. Jung;A. Hansson;N. Wehn
在从移动的设备到服务器的系统中，DRAM对性能有很大的影响，并占总功耗的很大一部分。系统的性能和功率取决于DRAM芯片的架构、存储器控制器的设计以及存储器控制器接收的访问模式。因此，评估DRAM设计决策的影响需要一种整体方法，包括DRAM存储体的适当模型、实际控制器和DRAM功率模型以及代表性工作负载，这需要运行完整软件栈的完整系统模拟器。在本文中，我们介绍了DRAMSpec，一个高层次的DRAM银行/芯片建模工具。我们的贡献是将DRAM建模抽象级别从电路级移动到DRAM库，并通过集成在完整的系统仿真器中，我们允许系统或处理器设计人员（非DRAM专家）为他们的目标应用调整未来的DRAM架构。我们证明了DRAMSpec的优点，通过探索DRAM行缓冲区（页面）的大小和银行的数量对性能和功率的服务器应用程序（memcached）的影响。我们的新DRAM设计提供了一个16%的DRAM性能提高和13%的DRAM节能相比，标准comodity DDR3设备。此外，我们演示了我们的工具是如何能够帮助评估新的DRAM架构，如混合存储器立方体（HMC），其中没有DRAM芯片。最后，我们强调了DRAM技术扩展为特定的HMC架构，我们量化的延迟和功耗的影响。
In systems ranging from mobile devices to servers, DRAM has a big impact on performance and contributes a significant part of the total consumed power. The performance and power of the system depends on the architecture of the DRAM chip, the design of the memory controller and the access patterns received by the memory controller. Thus, evaluating the impact of DRAM design decisions requires a holistic approach that includes an appropriate model of the DRAM bank, a realistic controller and DRAM power model, and a representative workload, which requires a full system simulator running a complete software stack. In this paper, we introduce DRAMSpec, a high-level DRAM bank/chip modeling tool. Our contribution is to move the DRAM modeling abstraction level from the circuit level to the DRAM bank and by the integration in full system simulators we allow system or processor designers (non-DRAM experts) to tune future DRAM architectures for their target applications. We demonstrate the merits of DRAMSpec by exploring the influence of DRAM row-buffer (page) size and the number of banks on performance and power of a server application (memcached). Our new DRAM design offers a 16% DRAM performance improvement and 13% DRAM energy saving compared to standard comodity DDR3 devices. Additionally, we demonstrate how our tool is able to aid in evaluating novel DRAM architectures, such as the Hybrid Memory Cube (HMC), for which no DRAM datasheets are available. Finally, we highlight the DRAM technology scaling for a specific HMC architecture and we quantify the impact on latency and power.
以数据为中心的工作负载的混合内存立方体性能表征
DOI：
10.1145/2833179.2833184
发表时间：
2015
期刊：
Proceedings of the 5th Workshop on Irregular Applications: Architectures and Algorithms
影响因子：
--
作者：
M. Gokhale;Scott Lloyd;C. Macaraeg
通讯作者：
C. Macaraeg
改进的 DDR SDRAM 功率建模
DOI：
10.1109/dsd.2011.17
发表时间：
2011
期刊：
2011 14th Euromicro Conference on Digital System Design
影响因子：
--
作者：
K. Chandrasekar;B. Akesson;K. Goossens
通讯作者：
K. Goossens
DRAM 器件组织：基本电路和架构
DOI：
10.1016/b978-012379751-3.50010-2
发表时间：
2008
期刊：
IEEE Transactions on Circuits and Systems I: Regular Papers
影响因子：
--
作者：
B. Jacob;S. Ng;David T. Wang
通讯作者：
David T. Wang