How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
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如何增强超标量处理器以提供硬实时功能的有序 SMT
DOI:
10.1007/978-3-642-11950-7_2
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发表时间:
2010
期刊:
影响因子:
--
通讯作者:
Theo Ungerer
中科院分区:
文献类型:
--
作者:
Jörg Mische;Irakli Guliashvili;Sascha Uhrig;Theo Ungerer
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-time applications. For superscalar in-order architectures the calculation of the Worst Case Execution Time (WCET) is much easier and tighter than for out-of-order architectures. By a careful enhancement that completely isolates the threads, this capability can be perpetuated to an in-order SMT architecture. Our design goal is to minimise the WCET of the highest priority thread, while releasing as many resources as possible for the execution of concurrent non critical threads. The resultant processor executes hard real-time threads at the same speed as its singlethreaded ancestor, but idle issue slots are dynamically used by non critical threads. The modifications to enable SMT are demonstrated by CarCore, a multithreaded embedded processor that implements the Infineon Tricore instruction set.
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影响因子:
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作者:
Stefan Metzlaff;S. Uhrig;Jörg Mische;T. Ungerer
通讯作者:
T. Ungerer
DOI:
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发表时间:
1999
期刊:
Proceedings Fifth International Symposium on High-Performance Computer Architecture
影响因子:
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作者:
S. Hily;André Seznec
通讯作者:
André Seznec
DOI:
--
发表时间:
2003
期刊:
J. Instr. Level Parallelism
影响因子:
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作者:
Gautham Thambidorai;D. Yeung;Seungryul Choi
通讯作者:
Seungryul Choi
DOI:
10.1109/real.2002.1181569
发表时间:
2002
期刊:
23rd IEEE Real-Time Systems Symposium, 2002. RTSS 2002.
影响因子:
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作者:
R. Jain;C. Hughes;S. Adve
通讯作者:
S. Adve
DOI:
10.1109/iccd.2008.4751887
发表时间:
2008
期刊:
2008 IEEE International Conference on Computer Design
影响因子:
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作者:
Jörg Mische;Sascha Uhrig;Florian Kluge;Theo Ungerer
通讯作者:
Theo Ungerer