How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT
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如何增强超标量处理器以提供硬实时功能的有序 SMT

DOI:
10.1007/978-3-642-11950-7_2
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发表时间:
2010
期刊:
影响因子:
--
通讯作者:
Theo Ungerer
Theo Ungerer
中科院分区:
--
文献类型:
--
作者:
Jörg Mische;Irakli Guliashvili;Sascha Uhrig;Theo Ungerer

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本文描述了如何修改超标量有序处理器以支持同时多线程(SMT),从而为硬实时应用保持时间可预测性。对于超标量有序体系结构,最坏情况执行时间(WCET)的计算比无序体系结构要容易得多,也更紧凑。通过仔细地增强以完全隔离线程,此功能可以在有序的SMT体系结构中保持不变。我们的设计目标是最小化最高优先级线程的WCET,同时为并发非关键线程的执行释放尽可能多的资源。得到的处理器以与其单线程祖先相同的速度执行硬实时线程,但空闲问题槽由非关键线程动态使用。CarCore是实现Infineon TriCore指令集的多线程嵌入式处理器,它演示了启用SMT的修改。
This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-time applications. For superscalar in-order architectures the calculation of the Worst Case Execution Time (WCET) is much easier and tighter than for out-of-order architectures. By a careful enhancement that completely isolates the threads, this capability can be perpetuated to an in-order SMT architecture. Our design goal is to minimise the WCET of the highest priority thread, while releasing as many resources as possible for the execution of concurrent non critical threads. The resultant processor executes hard real-time threads at the same speed as its singlethreaded ancestor, but idle issue slots are dynamically used by non critical threads. The modifications to enable SMT are demonstrated by CarCore, a multithreaded embedded processor that implements the Infineon Tricore instruction set.
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DOI: --
发表时间: 2008
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