Physical Design of Monolithic 3 D ICs with Applications to Hardware Security
Physical Design of Monolithic 3 D ICs with Applications to Hardware Security
复制标题
单片 3D IC 的物理设计及其在硬件安全方面的应用
DOI：
--
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
E. Salman
中科院分区：
文献类型：
--
作者：
Chen Yan;E. Salman
单片3D集成电路提供垂直互连，其尺寸与片上金属通孔相当，因此实现了超高密度的设备集成。提出了一个自定义单元库和设计流程来开发完全放置和路由的单片3D集成电路。展示了一个128点的单片3D实现，具有大约330K个单元的高度并行FFT核心。单片3D技术对功率、占地面积和性能的影响是量化的。此外，所提出的设计套件和单元库被用来评估电路伪装对系统功率、延迟和面积的影响。开发了一种伪装轻量级分组密码SIMON。gds级仿真结果表明，单片三维技术能够有效地利用伪装技术抵御基于图像分析的逆向工程攻击。单片3D技术的代价是时间特性略有下降，不仅消除了面积，而且还减少了与伪装相关的功率开销。关键词：单片机三维集成；三维细胞库；3D硬件安全；电路伪装;逆向工程
Monolithic 3D ICs provide vertical interconnects with comparable size to on-chip metal vias and therefore achieve ultra-high density device integration. A custom cell library and design flow are proposed to develop fully placed and routed monolithic 3D ICs. A monolithic 3D implementation of a 128point, highly parallelized FFT core with approximately 330K cells is demonstrated. The effects of monolithic 3D technology on power, footprint, and performance are quantified. Furthermore, the proposed design kit and cell libraries are utilized to evaluate the effects of circuit camouflaging on system power, delay, and area. A camouflaged lightweight block cipher, SIMON, is developed. GDS-level simulation results demonstrate that the monolithic 3D technology is highly effective to facilitate the utilization of camouflaging technique against image analysis based reverse engineering attacks. At the expense of a slight degradation in timing characteristics, monolithic 3D technology eliminates not only the area, but also the power overhead related to camouflaging. Keywords—Monolithic 3D integration; 3D cell library; 3D hardware security; circuit camouflaging; reverse engineering
DOI：
10.1109/tcsii.2017.2749523
发表时间：
2018-06
期刊：
IEEE Transactions on Circuits and Systems II: Express Briefs
影响因子：
--
作者：
Chen Yan;Jaya Dofe;Scott Kontak;Qiaoyan Yu;E. Salman
通讯作者：
Chen Yan;Jaya Dofe;Scott Kontak;Qiaoyan Yu;E. Salman