A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder
A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder
复制标题
用于 HEVC 解码器的紧凑型 32 像素面向 TU 且无 SRAM 的帧内预测 VLSI 架构
DOI:
10.1109/access.2019.2946907
复制
发表时间:
2019
期刊:
影响因子:
3.9
通讯作者:
Xiaoyang Zeng
中科院分区:
文献类型:
--
作者:
Yibo Fan;Genwei Tang;Xiaoyang Zeng
In the High Efficiency Video Coding (HEVC), a variety of CU sizes and intra prediction modes significantly improve coding efficiency, but also bring higher computational complexity. This paper proposes a new compact VLSI architecture for HEVC intra prediction, which is geared towards 8K video decoding. It supports all the transform unit (TU) sizes and 35 HEVC intra prediction modes. First, this paper introduces a TU-oriented intra predictor with a throughput of 32 pixels, which can be newly arranged with the TU size. It can be a line of 32 pixels, two lines of 16 pixels, 4 lines of 8 pixels or four lines of four pixels. This TU-oriented architecture allows intra-prediction and inverse discrete cosine transform (IDCT) to be computed in parallel, removing the memory between them. In addition, a horizontal and vertical line buffer for reference sample is proposed, which only cost 0.8K bit and is implemented by register files with SRAM-free. Finally, to further reduce hardware consumption, multipliers can be shared in the prediction. The implementation result shows that the compact architecture supports 8K video application and costs 66.2K logic gates, which is synthesized with the TSMC 65nm process under 400MHz.
DOI:
10.1109/tcsvt.2003.815165
发表时间:
2003-07-01
影响因子:
8.4
作者:
Wiegand, T;Sullivan, GJ;Luthra, A
通讯作者:
Luthra, A
DOI:
10.1109/vcip.2014.7051538
发表时间:
2014-12
期刊:
2014 IEEE Visual Communications and Image Processing Conference
影响因子:
--
作者:
Heming Sun;Dajiang Zhou;Jiayi Zhu;S. Kimura;S. Goto
通讯作者:
Heming Sun;Dajiang Zhou;Jiayi Zhu;S. Kimura;S. Goto