Statistical DRAM modeling
Statistical DRAM modeling
复制标题
统计 DRAM 建模
DOI：
10.1145/3357526.3357576
复制
发表时间：
2019
期刊：
影响因子：
--
通讯作者：
Jacob, Bruce
中科院分区：
文献类型：
--
作者：
Li, Shang;Jacob, Bruce
周期精确的DRAM模型在当今的计算机体系结构模拟中很普遍。然而，周期精确模型的设计是耗时的，不可扩展的。在本文中，我们提出了一种统计方法的DRAM延迟建模。与以前的作品不同，我们的方法将DRAM延迟建模转换为分类问题，并采用机器学习模型，如决策树和随机森林来解决分类问题。我们提出了4个基本的DRAM延迟类，以简化和参数化的分类，并提取功能，帮助分类从内存请求流的飞行。我们使用合成轨迹来训练统计模型，并在真实世界的基准测试中测试模型的准确性和速度。结果表明，我们的统计模型将DRAM模拟速度提高了400倍，对于我们测试的所有基准测试，平均分类准确率为98%。
Cycle-accurate DRAM models are prevalent in today's computer architecture simulations. However, cycle-accurate models by design are time consuming and not scalable. In this paper, we present a statistical approach of DRAM latency modeling. Unlike previous works, our approach converts DRAM latency modeling into a classification problem and employ machine learning models such as decision tree and random forest to solve the classification problem. We propose 4 basic DRAM latency classes to simplify and parameterize the classification, and extract features that help classification from memory request streams on the fly. We use synthetic traces to train the statistical model and test the model on real-world benchmarks in both accuracy and speed against a cycle-accurate simulator. The results show our statistical models improves the DRAM simulations speed by up to 400 times with 98% average classification accuracy for all the benchmarks we have tested.
影响因子：
3.6
作者：
Wolf, C.;Bruess, M.;Molderings, G. J.
通讯作者：
Molderings, G. J.
自动构建内存控制器的周期近似事务级模型
DOI：
10.1109/date.2012.6176653
发表时间：
2012
期刊：
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)
影响因子：
--
作者：
V. Todorov;Daniel Mueller;H. Reinig;Ulf Schlichtmann
通讯作者：
Ulf Schlichtmann