Gate delay modeling with multiple input switching for static (statistical) timing analysis
Gate delay modeling with multiple input switching for static (statistical) timing analysis
复制标题
具有多输入切换的栅极延迟建模，用于静态（统计）时序分析
DOI：
10.1109/vlsid.2006.92
复制
发表时间：
2006
期刊：
影响因子：
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通讯作者：
Tom Chen
中科院分区：
文献类型：
--
作者：
J. Sridharan;Tom Chen
随着现代VLSI设计的工作频率的增加以及相对于标称工艺参数的工艺变化的增加，多输入切换的机会已经增加。传统的静态时序分析方法假设单输入开关不再足以捕捉门级延迟。我们提出了一种新的方法，系统地建模门延迟使用高维模型表示（HDMR）模型。所提出的方法建模门延迟相对于其输入的相对信号到达时间（RSAT）。由此产生的门延迟模型可以用于门级静态时序分析。所提出的算法的系统性，允许门延迟特性与多个输入切换多达5个输入被报告的第一次。所提出的模型进行了扩展，以允许输入信号的斜率和过程的变化被考虑到统计静态时序分析。我们的研究结果表明，建议的HDMR模型给出了2.2%至9.3%之间的误差相比，SPICE的结果取决于在开关所涉及的输入的数量。
With increase in operating frequency of modern VLSI designs and increase in process variations relative to the nominal process parameters, the chances of multiple input switching have increased. The traditional method of static timing analysis assuming single input switching is no longer adequate enough to capture gate level delays. We propose a new method of systematically modeling gate delays using the high dimensional model representation (HDMR) model. The proposed method models gate delays with respect to the relative signal arrival times (RSAT) of its inputs. The resulting gate delay models can be used for gate-level static timing analysis. The systematic nature of the proposed algorithm allows gate delay characterization with multiple input switching of up to 5 inputs to be reported for the first time. The proposed model is extended to allow the input signal slope and process variations to be taken into account for statistical static timing analysis. Our results show that the proposed HDMR model gives an error between 2.2% to 9.3% compared to SPICE results depending on the number of inputs involved in switching.
DOI：
10.11203/jar.19.177
发表时间：
2004-09
期刊：
--
影响因子：
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作者：
裕幸 飯田;菊男 竹田;武利 藤本
通讯作者：
裕幸 飯田;菊男 竹田;武利 藤本