A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme
A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme
复制标题
适用于太阳能供电便携式个人数字设备的 0.5V 25MHz 1mW 256kb MTCMOS/SOI SRAM - 通过使用降压负过驱动位线方案确保写入操作
DOI：
10.1109/jssc.2005.864124
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发表时间：
2006
影响因子：
5.4
通讯作者：
T. Douseki
中科院分区：
文献类型：
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作者：
N. Shibata;Hiroshi Kiya;Shigehiro Kurita;Hidetaka Okamoto;Masa'aki Tan'no;T. Douseki
多阈值电压CMOS（MTCMOS）技术具有很大的优势，因为它在小于1 V的低电源电压下提供高速操作。具有低V/sub th/MOSFET的逻辑门具有高操作速度，而具有高V/sub th/ MOSFET的低泄漏功率开关消除了睡眠时间期间的关断泄漏电流。利用MTCMOS电路和SOI器件，研制了一种适用于太阳能数字设备的256 kb SRAM。功率开关管采用双阈值电压MOSFET（DTMOS），进一步降低了关断漏电流。至于SRAM内核设计，我们考虑了由高V/sub th/和低V/sub th/MOSFET（即多V/sub th/ CMOS）组成的混合配置。具有单独的读取数据路径的新的存储器单元提供更大的读出电流而不降低静态噪声容限。一个负过驱动的NAND计划保证在超低电源电压接近0.5 V的写操作。此外，一个电荷转移放大器集成了一个选择器和数据锁存器的intrabus电路安装，以提高工作速度和/或降低功耗。采用0.35 μ m/spl μ m multi-V/sub th/ CMOS/SOI工艺制造的32 K字/spl次/ 8位SRAM芯片，在典型的0.5V（SRAM内核）和1V（I/O缓冲器）电源下，工作频率为25 MHz。休眠期间的功耗小于0.4 /spl mu/W，25 MHz工作时的功耗为1 mW（不包括I/O缓冲器）。
Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.
DOI：
10.1109/jssc.2003.813248
发表时间：
2003-07
期刊：
IEEE J. Solid State Circuits
影响因子：
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作者：
T. Enomoto;Yoshinori Oka;H. Shikano
通讯作者：
T. Enomoto;Yoshinori Oka;H. Shikano