Energy Optimization in 3D Networks-on-Chip through Dynamic Voltage Scaling technique
Energy Optimization in 3D Networks-on-Chip through Dynamic Voltage Scaling technique
复制标题
通过动态电压调节技术实现 3D 片上网络的能量优化
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
H. Shahhoseini
中科院分区：
文献类型：
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作者：
M. Momeni;H. Shahhoseini
片上网络（Network-on-Chips，NoCs）消耗了整个系统能量预算的很大一部分。三维NoC作为众核系统中可行的架构克服了通信需求，在面积、延迟、性能和可扩展性方面优于二维NoC，然而，三维NoC消耗的功率甚至比二维NoC更高。在路由器和链路中使用电压缩放技术可以显著提高节能效果。不幸的是，电压电平的降低损害了延迟和通信可靠性。由于新兴应用可以容忍输出的不准确性，并且由于3D NoC的延迟减少，动态电压缩放（DVS）技术被应用于3D NoC的链路和路由器以应对容错通信。因此，能量效率和性能在3D NoC中得到显著改善，同时输出在可接受的方差内。仿真结果表明，所描述的方法提高了平均27%的能源效率在不同的PARSEC基准。
Networks-on-Chips (NoCs) consume the large fraction of the whole system energy budget. Three-dimensional NoCs overcome the communication demands as a viable architecture in many-core systems, outperform 2D NoCs in terms of area, latency, performance and scalability, however, 3D NoCs consume high power even more than 2D NoCs. Using the voltage scaling technique in routers and links can significantly improve energy saving. Unfortunately, voltage level reduction compromises the latency and the communication reliability. As emerging applications can tolerate inaccuracy in the output and due to the latency reduction in 3D NoCs, Dynamic Voltage Scaling (DVS) technique is applied to the links and routers of 3D NoC in facing with error tolerance communications. Therefore, energy efficiency and the performance are significantly improved in 3D NoC while outputs are within an acceptable variance. Simulation results indicate that the described method improves on average the energy efficiency 27% across different PARSEC benchmarks.
DOI：
10.1109/iccd.2018.00078
发表时间：
2018-10
期刊：
2018 IEEE 36th International Conference on Computer Design (ICCD)
影响因子：
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作者：
Yuechen Chen;Md Farhadur Reza;A. Louri
通讯作者：
Yuechen Chen;Md Farhadur Reza;A. Louri