Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs

Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs
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适用于 FPGA 上 DSP 应用的混合二元-一元截断乘法

DOI:
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发表时间:
2020
期刊:
2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
影响因子:
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通讯作者:
K. Bazargan
K. Bazargan
中科院分区:
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文献类型:
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作者:
S. R. Faraji;K. Bazargan

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乘法器是现代DSP系统的基本组成部分,对系统的整体性能有重要影响。在许多DSP系统中,使用截断乘法器而不是全精度乘法器可以将精度保持在理想的水平,同时显著降低FPGA资源、延迟和功耗。截断乘法器广泛用于加速DSP应用,如滤波、快速傅立叶和离散余弦变换。在本文中,我们提出了一种新的低成本,低能量,和高速截断乘法器使用混合二进制一进制编码方法。我们利用一元计算的方法,利用两个错误校正机制,以减少错误,而不增加硬件成本。所提出的乘法器在硬件成本方面优于Xilinx LogiCORE IP,在精度和硬件成本方面优于最先进的FPGA专用近似乘法器。所提出的近似乘法器的面积减少12%至48%之间的7至15位乘法器的平均。我们评估的FIR滤波器,2-D离散余弦变换,快速傅立叶变换作为三种常见的DSP算法的性能建议乘法器。评估结果表明,这些应用程序可以提供理想的性能使用建议的乘数。
Multipliers are the basic building blocks of modern DSP systems and contribute significantly to their overall performance. In many DSP systems, using truncated multipliers instead of full precision multipliers can keep the accuracy at a desirable level while significantly reducing FPGA resources, delay, and power consumption. Truncated multipliers are widely used to accelerate DSP applications such as filtering, fast Fourier, and discrete cosine transforms. In this paper we propose a novel low-cost, low energy, and highspeed truncated multiplier using a hybrid binary-unary encoding method. We take advantage of the unary computing method to exploit two error correction mechanisms in order to reduce error without adding to the hardware cost. The proposed multipliers outperform Xilinx LogiCORE IP in terms of hardware cost, and outperform state-of-the-art FPGA-specific approximate multipliers in terms of accuracy and hardware costs. The proposed approximate multipliers result in area reductions between 12% to 48% for 7- to 15-bit multipliers on average. We assess the performance of the proposed multipliers on an FIR filter, 2-D discrete cosine transform, and fast Fourier transform as three common DSP algorithms. The evaluation results show that these applications can deliver desirable performance using the proposed multipliers.
DOI: 10.1145/2966986.2967005
发表时间: 2016-11
期刊: 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
影响因子: --
作者:
Semeen Rehman;Walaa El-Harouni;M. Shafique;Akash Kumar;J. Henkel
通讯作者: Semeen Rehman;Walaa El-Harouni;M. Shafique;Akash Kumar;J. Henkel