Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs
Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs
复制标题
适用于 FPGA 上 DSP 应用的混合二元-一元截断乘法
DOI:
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发表时间:
2020
期刊:
影响因子:
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通讯作者:
K. Bazargan
中科院分区:
文献类型:
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作者:
S. R. Faraji;K. Bazargan
Multipliers are the basic building blocks of modern DSP systems and contribute significantly to their overall performance. In many DSP systems, using truncated multipliers instead of full precision multipliers can keep the accuracy at a desirable level while significantly reducing FPGA resources, delay, and power consumption. Truncated multipliers are widely used to accelerate DSP applications such as filtering, fast Fourier, and discrete cosine transforms. In this paper we propose a novel low-cost, low energy, and highspeed truncated multiplier using a hybrid binary-unary encoding method. We take advantage of the unary computing method to exploit two error correction mechanisms in order to reduce error without adding to the hardware cost. The proposed multipliers outperform Xilinx LogiCORE IP in terms of hardware cost, and outperform state-of-the-art FPGA-specific approximate multipliers in terms of accuracy and hardware costs. The proposed approximate multipliers result in area reductions between 12% to 48% for 7- to 15-bit multipliers on average. We assess the performance of the proposed multipliers on an FIR filter, 2-D discrete cosine transform, and fast Fourier transform as three common DSP algorithms. The evaluation results show that these applications can deliver desirable performance using the proposed multipliers.
DOI:
10.1145/2966986.2967005
发表时间:
2016-11
期刊:
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
影响因子:
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作者:
Semeen Rehman;Walaa El-Harouni;M. Shafique;Akash Kumar;J. Henkel
通讯作者:
Semeen Rehman;Walaa El-Harouni;M. Shafique;Akash Kumar;J. Henkel