Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective
复制标题
真正剥离逻辑锁定的功能：基于故障的视角
DOI：
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复制
发表时间：
2020
影响因子：
2.9
通讯作者：
O. Sinanoglu
中科院分区：
文献类型：
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作者：
A. Sengupta;M. Nabeel;Nimisha Limaye;M. Ashraf;O. Sinanoglu
逻辑锁定是应对制造威胁的整体解决方案，例如知识产权 (IP) 盗版和硬件级别的过度建设。然而，多年的研究暴露了锁定的各种缺陷，包括基于布尔可满足性 (SAT) 的攻击。因此，已经提出了几种 SAT 弹性锁定技术，例如 SARLock、Anti-SAT 和 SFLL，尽管其中的某些实例也被一类称为删除攻击的攻击所破坏。在本文中，我们通过利用超大规模集成（VLSI）测试中的众所周知的原理来实现逻辑锁定，并得出逻辑锁定属性，这些属性决定了锁定技术针对不同攻击的弹性。我们提出了 SFLL 的修订版本，即 SFLL-rem，它不仅保留了 SFLL 的所有安全属性，为 SFLL 可以阻止的所有最先进的攻击提供弹性，而且还针对破坏某些 SFLL 实例的最新删除攻击。此外，我们开发了一个与行业工具集成的安全感知 CAD 框架，该框架在功耗、性能和面积方面分别仅产生 -1.5%、0% 和 4.13% 的开销。我们在 65 nm ARM Cortex-M0 微处理器上演示了 SFLL-rem 的硅实现。此外，我们为SoC设计人员提供了一个框架，可以根据SoC模块及其威胁模型定制逻辑锁定；通过锁定 DARPA 提供的数百万门 SoC 并将该 SoC 一直采用 GDSII 布局来说明这一点。
Logic locking is a holistic solution to counter manufacturing threats, such as intellectual property (IP) piracy and overbuilding at the hardware level. However, years of research has exposed various flaws in locking, including a Boolean satisfiability (SAT)-based attack. Consequently, several SAT-resilient locking techniques, such as SARLock, Anti-SAT, and SFLL have been proposed, although certain instances of them have also been broken by a class of attacks, called removal attack. In this article, we approach logic locking by leveraging well-known principles from very large-scale integration (VLSI) testing and elicit logic locking properties that dictate the resilience of a locking technique against different attacks. We present a revised version of SFLL, namely SFLL-rem, that not only retains all security properties of SFLL, delivering resilience to all the state-of-the-art attacks SFLL can thwart, but also to the latest removal attacks that broke some SFLL instances. Further, we develop a security-aware CAD framework integrated with industry tools that incurs only −1.5%, 0%, and 4.13% overhead for power, performance, and area, respectively. We demonstrate a silicon implementation of SFLL-rem on ARM Cortex-M0 microprocessor in 65 nm. Moreover, we provide a framework for an SoC designer to customize logic locking based on the SoC blocks and their threat models; this is illustrated by locking a multimillion-gate SoC provided by DARPA, and taking the SoC all the way to GDSII layout.
DOI：
10.1109/iccad.2017.8203759
发表时间：
2017-11
期刊：
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
影响因子：
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作者：
H. Zhou;Ruifeng Jiang;Shuyu Kong
通讯作者：
H. Zhou;Ruifeng Jiang;Shuyu Kong
DOI：
10.1145/3060403.3060469
发表时间：
2017-05
期刊：
Proceedings of the Great Lakes Symposium on VLSI 2017
影响因子：
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作者：
Yuanqi Shen;H. Zhou
通讯作者：
Yuanqi Shen;H. Zhou