Resistive Open Defect Classification of Embedded Cells under Variations

Resistive Open Defect Classification of Embedded Cells under Variations
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变化下嵌入式电池的电阻开路缺陷分类

DOI:
10.1109/lats53581.2021.9651857
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发表时间:
2021
期刊:
2021 IEEE 22nd Latin American Test Symposium (LATS)
影响因子:
--
通讯作者:
H. Wunderlich
H. Wunderlich
中科院分区:
--
文献类型:
--
作者:
Zahra Paria Najafi;H. Wunderlich

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小延迟故障(SDF)由于缺陷和边际必须从额外的延迟由于工艺变化区分,因为它们可能会形成一个可靠性威胁,即使产生的时间是在规范。本文表明,即使相应的缺陷单元深深嵌入到组合电路中并且其行为特征受到电路其余部分的几种掩蔽影响,这些故障仍然可以被识别。在不同电压和频率下的一些延迟测试的结果作为机器学习程序的输入,机器学习程序可以将电路分类为由于缺陷而边缘化或由于变化而缓慢。研究了几种机器学习技术,并比较了不同电路尺寸和缺陷规模的准确度,精度和召回率。分类策略足够强大,可以在不对良率产生重大影响的情况下分选出缺陷器件。
Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is in the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its behavioral features are affected by several masking impacts of the rest of the circuit. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defect devices without a major impact on yield.
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