Forward-Projection Architecture for Fast Iterative Image Reconstruction in X-ray CT.

Forward-Projection Architecture for Fast Iterative Image Reconstruction in X-ray CT.
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DOI:
10.1109/tsp.2012.2208636
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发表时间:
2012-10
期刊:
IEEE transactions on signal processing : a publication of the IEEE Signal Processing Society
影响因子:
--
通讯作者:
Zhang Z
Zhang Z
中科院分区:
其他
文献类型:
--
作者:
Kim JK;Fessler JA;Zhang Z

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迭代图像重建可以显著提高X射线计算机断层扫描(CT)中的图像质量,但计算涉及3D正投影和反投影的迭代步骤,这阻碍了常规临床使用。为了加速前向投影,我们分析了CT的几何形状,以确定内在的并行性和数据访问序列的高度并行的硬件架构。为了提高这种架构的效率,我们提出了一个注水缓冲区,以消除流水线失速,和一个无序的扇区处理,以减少片外存储器访问高达三个数量级。我们做了一个浮点到定点的转换的基础上的数值模拟,并表现出可比的图像质量在一个低得多的实现成本。作为概念验证,在Xilinx Virtex-5 FPGA上原型化了5级完全流水线化的55路并行可分离足迹前向投影仪,在200 MHz时钟频率下的吞吐量为9.258亿体素投影/s,比在8核2.8 GHz CPU上运行的优化的16线程程序高4.6倍。类似的架构可以应用于完整的迭代图像重建系统的反投影。所提出的算法和架构也可以应用于硬件平台,如图形处理器和数字信号处理器,以实现显着的加速。
Iterative image reconstruction can dramatically improve the image quality in X-ray computed tomography (CT), but the computation involves iterative steps of 3D forward- and back-projection, which impedes routine clinical use. To accelerate forward-projection, we analyze the CT geometry to identify the intrinsic parallelism and data access sequence for a highly parallel hardware architecture. To improve the efficiency of this architecture, we propose a water-filling buffer to remove pipeline stalls, and an out-of-order sectored processing to reduce the off-chip memory access by up to three orders of magnitude. We make a floating-point to fixed-point conversion based on numerical simulations and demonstrate comparable image quality at a much lower implementation cost. As a proof of concept, a 5-stage fully pipelined, 55-way parallel separable-footprint forward-projector is prototyped on a Xilinx Virtex-5 FPGA for a throughput of 925.8 million voxel projections/s at 200 MHz clock frequency, 4.6 times higher than an optimized 16-threaded program running on an 8-core 2.8-GHz CPU. A similar architecture can be applied to back-projection for a complete iterative image reconstruction system. The proposed algorithm and architecture can also be applied to hardware platforms such as graphics processing unit and digital signal processor to achieve significant accelerations.
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