GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors

GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors
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GreenFlag:保护 3D 赛道内存免受移位错误的影响

DOI:
10.1109/dsn.2019.00016
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发表时间:
2019
期刊:
49th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2019
影响因子:
--
通讯作者:
Sorin, Daniel J.
Sorin, Daniel J.
中科院分区:
--
文献类型:
--
作者:
Mappouras, Georgios;Vahid, Alireza;Calderbank, Robert;Sorin, Daniel J.

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赛道存储器是一种令人兴奋的新兴存储器技术,有可能提供比其他非易失性存储器更大的容量和性能。不过,Racetrack内存有一个不寻常的错误模型,它排除了架构师使用的典型错误编码技术。在本文中,我们介绍了GreenFlag,一种编码方案,结合了一个新的构造Varshamov-Tenegolts码与特制的bits之间放置在每个码字。GreenFlag是第一个与3D赛道兼容的编码方案,它具有非常高的密度,但每个赛道只有一个读/写端口的限制。基于我们的编码/解码硬件的实现,我们分析延迟,代码长度和码率之间的权衡,然后我们使用这种分析来评估赛道的可行性在每个级别的内存层次结构。
Racetrack memory is an exciting emerging memory technology with the potential to offer far greater capacity and performance than other non-volatile memories. Racetrack memory has an unusual error model, though, which precludes the use of the typical error coding techniques used by architects. In this paper, we introduce GreenFlag, a coding scheme that combines a new construction for Varshamov-Tenegolts codes with specially crafted delimiter bits that are placed between each codeword. GreenFlag is the first coding scheme that is compatible with 3D racetrack, which has the benefit of very high density but the limitation of a single read/write port per track. Based on our implementation of encoding/decoding hardware, we analyze the trade-offs between latency, code length, and code rate; we then use this analysis to evaluate the viability of racetrack at each level of the memory hierarchy.
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