Hardware Synthesis of Weakly Consistent C Concurrency
Hardware Synthesis of Weakly Consistent C Concurrency
复制标题
弱一致性C并发的硬件综合
DOI:
10.1145/3020078.3021733
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发表时间:
2017
期刊:
影响因子:
--
通讯作者:
Ramanathan N
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文献类型:
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作者:
Ramanathan N
Lock-free algorithms, in which threads synchronise not via coarse-grained mutual exclusion but via fine-grained atomic operations ('atomics'), have been shown empirically to be the fastest class of multi-threaded algorithms in the realm of conventional processors. This paper explores how these algorithms can be compiled from C to reconfigurable hardware via high-level synthesis (HLS). We focus on the scheduling problem, in which software instructions are assigned to hardware clock cycles. We first show that typical HLS scheduling constraints are insufficient to implement atomics, because they permit some instruction reorderings that, though sound in a single-threaded context, demonstrably cause erroneous results when synthesising multi-threaded programs. We then show that correct behaviour can be restored by imposing additional intra-thread constraints among the memory operations. We implement our approach in the open-source LegUp HLS framework, and provide both sequentially consistent (SC) and weakly consistent ('weak') atomics. Weak atomics necessitate fewer constraints than SC atomics, but suffice for many concurrent algorithms. We confirm, via automatic model-checking, that we correctly implement the semantics defined by the 2011 revision of the C standard. A case study on a circular buffer suggests that circuits synthesised from programs that use atomics can be 2.5x faster than those that use locks, and that weak atomics can yield a further 1.5x speedup.
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DOI:
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发表时间:
2006
期刊:
2006 IEEE International Conference on Field Programmable Technology
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发表时间:
2013
期刊:
2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines
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