10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed-signal adaption in 65 nm CMOS technology
10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed-signal adaption in 65 nm CMOS technology
复制标题
具有推测决策反馈均衡器的 10 Gbit/s 串行链路接收器，采用 65 nm CMOS 技术中的混合信号自适应
DOI：
10.1049/el.2015.1318
复制
发表时间：
2015-10
影响因子：
1.1
通讯作者：
Zhihua Wang
中科院分区：
文献类型：
--
作者：
Shuai Yuan;Ziqiang Wang;Xuqiang Zheng;Wen Jia;Liji Wu;Chuan Zhang;Zhihua Wang
提出了一种具有偏移校准连续时间线性均衡器、自适应单抽头半速率推测决策反馈均衡器（DFE）和基于相位插值器的时钟和数据恢复的10gbit /s串行链路接收机。采用一种新颖的符号-符号最小均方算法的混合信号实现了DFE的自适应，从而节省了硬件成本和功耗。该接收机采用65nm CMOS技术，在误码率为10−12的情况下，可以完全补偿24.85 dB的信道损耗。有源芯片面积为0.08 mm2, 1.2 V电源的总功耗为57 mW。
A 10 Gbit/s serial link receiver with an offset-calibrated continuous-time linear equaliser, an adaptive one-tap half-rate speculative decision feedback equaliser (DFE) and a phase-interpolator-based clock and data recovery is presented. Adaption of the DFE is achieved by using a novel mixed-signal implementation of the sign-sign least mean square algorithm to save the cost of hardware and power. Fabricated in 65 nm CMOS technology, the receiver can totally compensate 24.85 dB channel loss at a bit error rate of 10−12. The active chip area is 0.08 mm2 and the total power consumption is 57 mW from a 1.2 V supply.
影响因子：
5.4
作者：
M. Pozzoni;S. Erba;P. Viola;M. Pisati;Emanuele Depaoli;D. Sanzogni;R. Brama;D. Baldi;M. Repossi;F. Svelto
通讯作者：
M. Pozzoni;S. Erba;P. Viola;M. Pisati;Emanuele Depaoli;D. Sanzogni;R. Brama;D. Baldi;M. Repossi;F. Svelto
影响因子：
5.4
作者：
G. Balamurugan;J. Kennedy;G. Banerjee;J. Jaussi;M. Mansuri;F. O’Mahony;B. Casper;R. Mooney
通讯作者：
G. Balamurugan;J. Kennedy;G. Banerjee;J. Jaussi;M. Mansuri;F. O’Mahony;B. Casper;R. Mooney
DOI：
10.1109/isscc.2009.4977371
发表时间：
2009
期刊：
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
影响因子：
--
作者：
Y. Hidaka;Weixin Gai;T. Horie;J. Jiang;Y. Koyanagi;H. Osone
通讯作者：
Y. Hidaka;Weixin Gai;T. Horie;J. Jiang;Y. Koyanagi;H. Osone