The Java Virtual Machine in retargetable, high-performance instruction set simulation
The Java Virtual Machine in retargetable, high-performance instruction set simulation
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可重定向、高性能指令集模拟中的 Java 虚拟机
DOI：
10.1145/2093157.2093161
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
R. Spallek
中科院分区：
文献类型：
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作者：
M. Kaufmann;Matthias Häsing;Thomas B. Preußer;R. Spallek
关于指令集仿真的两个主要要求是可移植性和高模拟性能。对于ISA原型（例如在ASIP设计过程中）的测试和基准测试，还需要模拟器为快速建模和重新审视其模拟目标提供重新定位性。
在本文中，我们介绍了在结合了这三个相互矛盾的要求的全系统指令集仿真框架中应用的技术。我们的框架是可重新定位的，可移植的，并提供了高模拟性能。它完全在Java中实现，并具有针对Java字节码在第一阶段的两阶段动态二进制翻译（DBT），并在第二阶段使用Java虚拟机作为外部代码后端。尽管DBT之类的最新技术的使用会产生较高的模拟性能，但该框架也独立于平台，并且可以在任何符合J2SE的Java运行时环境上运行。尽管具有这种平台独立性，但第二阶段中生成的本机代码甚至将从现代JVM实现的平台特定优化中获利。我们的第二个贡献是HPADL，这是指令集说明语言，可提供我们框架的可重新定位性。 HPADL是针对动态编译全系统的特定需求而量身定制的。由于指令解码和指令执行之间的关注点清晰分开，因此可以轻松实现DBT。同样，它不仅限于特定的目标架构，例如RISC。在本文中，我们将将HPADL中的建模工作与Qemu的建模工作进行比较。为了进行实验，为了显示我们方法的实用性和灵活性，我们实施了DLX，8086，ARMV4和PowerPC/PowerPC/PowerPC VLE ISA的HPADL模型以及Java中的一些IO设备模型。通过引用EEMBC AutoBench 1.1的QEMU模拟性能的比较表明，我们平均达到了QEMU性能的78％。
Two main demands on instruction set simulation are portability and high simulation performance. For the testing and benchmarking of ISA prototypes such as in an ASIP design process, simulators are additionally required to offer retargetability for the rapid modeling and revisal of their simulation targets.
In this paper, we present the techniques applied in a full-system instruction set simulation framework that combines these three conflicting demands. Our framework is retargetable, portable and provides high simulation performance. It is entirely implemented in Java and features a two-stage dynamic binary translation (DBT) targeting Java Bytecode in the first stage and employing the Java Virtual Machine as an external code generation back end in the second stage. While the use of state-of-the-art techniques such as DBT generates high simulation performance, the framework is also platform independent and can run on any J2SE-compliant Java Runtime Environment. In spite of this platform independence, the native code generated in the second stage will even profit from the platform-specific optimizations performed by modern JVM implementations. Our second contribution is HPADL, the instruction set description language that provides the retargetability of our framework. HPADL is tailored for the specific needs of dynamically compiling full-system IS simulation. Due to its clean separation of concerns between the instruction decoding and instruction execution, it easily enables DBT. Also, it is not restricted to a specific range of target architectures such as RISC. In this paper, we will compare the modeling effort in HPADL to that of QEMU. For our experiments and in order to show the practicability and flexibility of our approach, we implemented HPADL models of the DLX, 8086, ARMv4 and PowerPC/PowerPC VLE ISA as well as some IO device models in Java. A comparison with the simulation performance of QEMU by reference of the EEMBC AutoBench 1.1 shows that we achieve 78% of the QEMU performance on average.
DOI：
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发表时间：
2023
期刊：
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影响因子：
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作者：
D. Brooks;V. Tiwari;Intel Margaret Martonosi
通讯作者：
D. Brooks;V. Tiwari;Intel Margaret Martonosi
考虑动态预成形的线驱动捕获机器人
DOI：
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发表时间：
2004
期刊：
第22回日本ロボット学会学術講演会予稿集
影响因子：
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作者：
M.Higashimori;東森 充;東森 充
通讯作者：
東森 充