MAC: a novel systematically multilevel cache replacement policy for PCM memory
MAC: a novel systematically multilevel cache replacement policy for PCM memory
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MAC：一种新颖的系统化 PCM 内存多级缓存替换策略
DOI：
10.5121/caij.2016.3202
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发表时间：
2016
期刊：
影响因子：
--
通讯作者：
Dongsheng Wang
中科院分区：
文献类型：
--
作者：
Shenchen Ruan;Haixia Wang;Dongsheng Wang
近年来，多核系统的快速发展和数据密集型应用的增加对内存提出了更高的要求。传统的DRAM存储器可以通过减小存储单元的特征尺寸来增加其容量。现在DRAM的进一步扩展面临着巨大的挑战，并且DRAM的频繁刷新操作会带来大量的能量消耗。相变存储器（PCM）作为一种新兴的存储技术，很有希望成为主存储器。它以其低功耗、高密度和非易失性等优点而受到广泛关注，但其持久性有限，写入延迟相对较长。针对写操作问题，通过优化该高速缓存替换策略来保护脏缓存块是一种有效的方法。在本文中，我们构建了一个系统的多级结构，并在此基础上提出了一种新的缓存替换策略称为MAC。MAC可以有效地减少PCM存储器的写流量，且硬件开销较低。我们在GEM5上进行了仿真实验，以评估MAC和其他相关工作的性能。结果表明，MAC在不增加程序执行时间的情况下，最大限度地减少了写操作量（平均为25.12%）。
The rapid development of multi-core system and increase of data-intensive application in recent years call for larger main memory. Traditional DRAM memory can increase its capacity by reducing the feature size of storage cell. Now further scaling of DRAM faces great challenge, and the frequent refresh operations of DRAM can bring a lot of energy consumption. As an emerging technology, Phase Change Memory (PCM) is promising to be used as main memory. It draws wide attention due to the advantages of low power consumption, high density and nonvolatility, while it incurs finite endurance and relatively long write latency. To handle the problem of write, optimizing the cache replacement policy to protect dirty cache block is an efficient way. In this paper, we construct a systematically multilevel structure, and based on it propose a novel cache replacement policy called MAC. MAC can effectively reduce write traffic to PCM memory with low hardware overhead. We conduct simulation experiments on GEM5 to evaluate the performances of MAC and other related works. The results show that MAC performs best in reducing the amount of writes (averagely 25.12%) without increasing the program execution time.
DOI：
10.11203/jar.19.177
发表时间：
2004-09
期刊：
--
影响因子：
--
作者：
裕幸 飯田;菊男 竹田;武利 藤本
通讯作者：
裕幸 飯田;菊男 竹田;武利 藤本