On-chip detection methodology for break-even time of power gated function units
On-chip detection methodology for break-even time of power gated function units
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电源门控功能单元盈亏平衡时间的片上检测方法
DOI：
10.1109/islped.2011.5993643
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
Hiroshi Nakamura
中科院分区：
文献类型：
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作者：
K. Usami;Yuya Goto;Kensaku Matsunaga;S. Koyama;Daisuke Ikebuchi;H. Amano;Hiroshi Nakamura
在对门控功能单元供电的细粒度泄漏节省技术中，效率对接通/关断电源开关时的开销能量耗散敏感。为了获得节能收益，断电时间必须长于最小所需时间，即盈亏平衡时间（BET）。虽然在文献中已经描述了BET感知功率门控控制的有效性，但是到目前为止还没有报道如何实际检测随着温度和工艺变化而波动的BET。本文提出了一种基于MTCMOS电路结构的pMOS/nMOS漏电流监测器的片上BET检测方法。我们采用这种方法的泄漏监控器和CPU，包括一个功率门控乘法器在65纳米CMOS技术实现。结果表明，我们的方法检测BET在5%-17%的差异，从传统的模拟为基础的离线技术。
In a fine-grain leakage saving technique to power gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off power switches. To get gain in energy savings, the powered-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware power-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far. This paper proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure. We applied this methodology to the leakage monitors and a CPU including a power-gated multiplier implemented in 65nm CMOS technology. Results showed that our methodology detects BET at 5%–17% difference from that of the conventional simulation-based off-line technique.
采用 MTCMOS 电路的片上漏电监测器的设计与分析
DOI：
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发表时间：
2008
期刊：
影响因子：
--
作者：
S.Koyama;S.Takeda;and K.Usami
通讯作者：
and K.Usami