Logic Locking Using Hybrid CMOS and Emerging SiNW FETs
Logic Locking Using Hybrid CMOS and Emerging SiNW FETs
复制标题
使用混合 CMOS 和新兴 SiNW FET 的逻辑锁定
DOI：
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复制
发表时间：
2017
期刊：
影响因子：
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通讯作者：
Yu Bi
中科院分区：
文献类型：
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作者：
Qutaiba Alasad;Jiann;Yu Bi
集成电路（IC）制造服务外包给海外制造代工厂，引起了关于知识产权（IP）保护的安全和隐私问题，以及制造芯片的完整性维护。保护ic免受恶意攻击的一种方法是通过合并额外的密钥门（即逻辑加密或逻辑锁定）来加密和混淆IP设计。最先进的逻辑加密技术肯定会在真正的IP设计上产生相当大的性能开销。本文的重点是利用新兴晶体管技术的独特特性来降低性能开销，并保持逻辑锁定技术的鲁棒性。我们使用硅纳米线场效应晶体管（SiNW fet）设计了多态逻辑门，以取代传统的异或逻辑锥。然后，我们根据安全度量和性能开销评估所建议的技术。
The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR (XOR)-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.
DOI：
10.1109/iccad.2017.8203759
发表时间：
2017-11
期刊：
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
影响因子：
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作者：
H. Zhou;Ruifeng Jiang;Shuyu Kong
通讯作者：
H. Zhou;Ruifeng Jiang;Shuyu Kong
DOI：
10.1145/3060403.3060469
发表时间：
2017-05
期刊：
Proceedings of the Great Lakes Symposium on VLSI 2017
影响因子：
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作者：
Yuanqi Shen;H. Zhou
通讯作者：
Yuanqi Shen;H. Zhou