Efficient Hardware Architecture for Sparse Coding
Efficient Hardware Architecture for Sparse Coding
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用于稀疏编码的高效硬件架构
DOI：
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发表时间：
2014
影响因子：
5.4
通讯作者：
Zhengya Zhang
中科院分区：
文献类型：
--
作者：
J. K. Kim;Phil C. Knag;Thomas Chen;Zhengya Zhang
稀疏编码使用少量被称为感受野的基函数对自然刺激进行编码。在这项工作中，我们设计了自定义的硬件架构，高效和高性能的稀疏编码算法称为稀疏和独立的本地网络（SAILnet）的实现。神经元尖峰动力学的研究揭示了重要的设计考虑，涉及神经网络的大小，目标发射率，神经元更新步长。这些参数的最佳调整保持神经元尖峰稀疏和随机，以实现最佳图像保真度。我们调查实用的硬件架构SAILnet：总线架构，提供高效的神经元通信，但导致尖峰冲突;和一个环架构，更具可扩展性，但导致神经元失火。我们表明，减少了稀疏尖峰神经网络的尖峰碰撞率，因此可以设计一个无仲裁总线架构，以容忍冲突，而不需要仲裁。为了减少神经元的误触发，我们设计了一个潜在的环结构来抑制神经元的反应，以提高图像的保真度。总线和环形架构可以组合在混合架构中，以实现高吞吐量和可扩展性。这三种架构是在65 nm CMOS工艺中合成和布局布线的。概念验证设计展示了高达每秒952 M像素的高稀疏编码吞吐量，每像素0.486 nJ的能耗。
Sparse coding encodes natural stimuli using a small number of basis functions known as receptive fields. In this work, we design custom hardware architectures for efficient and high-performance implementations of a sparse coding algorithm called the sparse and independent local network (SAILnet). A study of the neuron spiking dynamics uncovers important design considerations involving the neural network size, target firing rate, and neuron update step size. Optimal tuning of these parameters keeps the neuron spikes sparse and random to achieve the best image fidelity. We investigate practical hardware architectures for SAILnet: a bus architecture that provides efficient neuron communications, but results in spike collisions; and a ring architecture that is more scalable, but causes neuron misfires. We show that the spike collision rate is reduced with a sparse spiking neural network, so an arbitration-free bus architecture can be designed to tolerate collisions without the need of arbitration. To reduce neuron misfires, we design a latent ring architecture to damp the neuron responses for an improved image fidelity. The bus and the ring architecture can be combined in a hybrid architecture to achieve both high throughput and scalability. The three architectures are synthesized and place-and-routed in a 65 nm CMOS technology. The proof-of-concept designs demonstrate a high sparse coding throughput up to 952 M pixels per second at an energy consumption of 0.486 nJ per pixel.
影响因子：
5.4
作者：
Painkras, Eustace;Plana, Luis A.;Furber, Steve B.
通讯作者：
Furber, Steve B.