Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube
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NoC 对 3D 堆叠存储器的性能影响:来自混合存储器立方体的见解

DOI:
10.1109/ispass.2018.00018
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发表时间:
2018
期刊:
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS
影响因子:
--
通讯作者:
Kim, Hyesoon
Kim, Hyesoon
中科院分区:
--
文献类型:
--
作者:
Hadidi, Ramyad;Asgari, Bahar;Young, Jeffrey;Ahmad Mudassar, Burhan;Garg, Kartikay;Krishna, Tushar;Kim, Hyesoon

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诸如混合存储器立方体(HMC)的三维(3D)堆叠存储器提供了用于通过将存储器和逻辑管芯集成在单个堆叠中来克服处理器和存储器之间的带宽墙的有前景的解决方案。这种存储器还利用片上网络(NoC)来连接其内部结构元件并实现可扩展性。NoC的这种新用途实现了许多好处,例如高带宽和存储器级并行性,并为高效的存储器处理技术创造了未来的可能性。然而,这种NoC集成在存储器访问延迟和带宽方面对3D堆叠存储器的性能特性的影响还没有被充分探索。本文解决了这一知识差距(i)通过表征HMC原型使用美光的AC-510加速器板,并揭示其访问延迟和带宽行为;(ii)通过调查这些行为对系统和软件级设计的影响。与传统的基于DDR的存储器相比,我们的研究揭示了NoC对当前和未来3D堆栈存储器的性能影响,并演示了基于分组的协议、内部排队特性、流量条件和HMC的其他独特功能如何影响应用程序的性能。
Three-dimensional (3D)-stacked memories, such as the Hybrid Memory Cube (HMC), provide a promising solution for overcoming the bandwidth wall between processors and memory by integrating memory and logic dies in a single stack. Such memories also utilize a network-on-chip (NoC) to connect their internal structural elements and to enable scalability. This novel usage of NoCs enables numerous benefits such as high bandwidth and memory-level parallelism and creates future possibilities for efficient processing-in-memory techniques. However, the implications of such NoC integration on the performance characteristics of 3D-stacked memories in terms of memory access latency and bandwidth have not been fully explored. This paper addresses this knowledge gap (i) by characterizing an HMC prototype using Micron's AC-510 accelerator board and by revealing its access latency and bandwidth behaviors; and (ii) by investigating the implications of such behaviors on system- and software-level designs. Compared to traditional DDR-based memories, our examinations reveal the performance impacts of NoCs for current and future 3D-stacked memories and demonstrate how the packet-based protocol, internal queuing characteristics, traffic conditions, and other unique features of the HMC affects the performance of applications.
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