Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector-猫眼课题宝

用于 CLIC 顶点检测器的电容耦合 HV/HR-CMOS 传感器芯片的表征

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2017

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作者：

I. Kremastiotis;I. Perić;S. Kulis;R. Sune;D. Dannheim;A. Fiergolski;D. Hynds;M. Campbell

有源传感器和读出ASIC之间的电容耦合已经在CLIC顶点探测器研究的框架内被考虑。CLICpix电容耦合像素探测器(C3PD)是一款采用商用180 nm HV-cmos工艺生产的高压cmos传感器芯片。该传感器被设计为连接到CLICPix2读出芯片。因此，它与读出芯片的尺寸匹配，具有128x128平方像素、25μm间距的矩阵。传感器芯片是用衬底电阻率的标准值(∼20Ωcm)生产的，在接收和测试电容耦合组件之前，它已在独立测试模式下进行了表征。单机测试结果表明，在功耗为5∼W/像素的情况下，其上升时间为μ20 ns。C3PD高压cmos传感器芯片的生产预计将采用更高的衬底电阻率晶片(∼20、80、200和1000Ωcm)。更高的衬底电阻率的预期好处将使用读出芯片的未来组件进行研究。

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments