State of the art low capture power methodology
State of the art low capture power methodology
复制标题
最先进的低捕获功率方法
DOI：
10.1109/test.2011.6139164
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
S. Talluto
中科院分区：
文献类型：
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作者：
Swapnil Bahl;R. Mattiuzzo;Shray Khullar;A. Garg;S. Graniello;Khader S. Abdel;S. Talluto
测试期间的功耗可能显著高于正常功能模式期间的功耗。本文提出了一种低功耗自动测试模式生成（ATPG）流程，用于管理当今功耗关键设计中的捕获功耗。它介绍了一种新的方法，顺序使片上时钟控制器，以产生精确的低功耗ATPG模式尊重设计的电源规格。该方法的有效性证明了几个工业设计，显示在测试模式下的电源问题。
Power consumption during test can be significantly higher than during normal functional mode. This paper presents a low power Automated Test Pattern Generation (ATPG) flow for managing capture power in today's power critical designs. It introduces a novel method for sequentially enabling the on-chip clock controllers to generate accurate low power ATPG patterns respecting the power specifications of the design. The effectiveness of the method is demonstrated on several industrial designs that show up power issues during test mode.
DOI：
10.1109/ats.2008.27
发表时间：
2008-11
期刊：
2008 17th Asian Test Symposium
影响因子：
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作者：
H. Furukawa;X. Wen;K. Miyase;Yuta Yamato;S. Kajihara;P. Girard;Laung-Terng Wang;M. Tehranipoor
通讯作者：
H. Furukawa;X. Wen;K. Miyase;Yuta Yamato;S. Kajihara;P. Girard;Laung-Terng Wang;M. Tehranipoor