Exact Logic and Fault Simulation in Presence of Unknowns

Exact Logic and Fault Simulation in Presence of Unknowns
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存在未知数时的精确逻辑和故障模拟

DOI:
10.1145/2611760
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发表时间:
--
期刊:
ACM Trans. Design Autom. Electr. Syst.
影响因子:
--
通讯作者:
Becker
Becker
中科院分区:
--
文献类型:
--
作者:
Kochte;Hillebrecht;Schubert;Wunderlich;Becker

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逻辑和故障模拟是电子设计自动化的关键技术。标准模拟算法的准确性受到未知值或X值的影响。这导致在一个悲观的高估的X值信号的电路和悲观低估的故障covery.This工作提出了有效的算法组合和时序逻辑以及固定和过渡延迟故障模拟是免费的任何模拟悲观主义存在的未知数。基于SAT的算法准确地分类所有信号状态。在故障模拟过程中,每个故障被准确地分为未检测到的,肯定检测到的,或可能检测到的。相对于目前在经典算法的未知数的悲观主义是在基准电路的实验结果进行了深入的研究。所提出的算法的适用性证明在较大的工业电路。结果表明,通过精确的分析,可以显着增加检测到的故障的数量,而不增加测试集的大小。
Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage.This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected.The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size.
受限符号求值快速且有用
DOI: --
发表时间: 1989
期刊: 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
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具有近似值的符号模拟
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发表时间: 2012
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