Modeling of CMOS Devices and Circuits on Flexible Ultrathin Chips
Modeling of CMOS Devices and Circuits on Flexible Ultrathin Chips
复制标题
柔性超薄芯片上 CMOS 器件和电路的建模
DOI：
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发表时间：
2017
影响因子：
3.1
通讯作者：
R. Dahiya
中科院分区：
文献类型：
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作者：
Anastasios Vilouras;H. Heidari;Shoubhik Gupta;R. Dahiya
柔性电子领域正在迅速发展。该芯片被用于解决许多应用的高性能要求。然而，由于缺乏合适的紧凑模型，模拟和预测由于弯曲引起的应力引起的器件/电路响应的变化仍然是一个挑战。这使得可弯曲电子器件的电路设计成为一项艰巨的任务。本文介绍了在这一方向的进展，通过压缩和拉伸应力的晶体管和简单的电路，如反相器与不同的沟道长度和方向的晶体管上的CMOS芯片的研究。在标准CMOS 0.18- $mu中器件和电路的不同设计 ext{m}$技术在两个分离的芯片中制造。将两个制作好的芯片减薄到20 ~ μ m ext{m}$，采用标准的研磨前切割技术步骤，然后进行CMOS后处理，以获得足够的弯曲性（20 mm弯曲半径或0.05%标称应变）。通过将减薄的芯片封装在柔性基板上来进行电特性表征。实验结果表明，在各个晶体管的载流子迁移率的变化，和开关阈值电压的反相器在不同的弯曲条件（最大百分比变化为2%的压缩和4%的拉伸应力）。为了模拟这些变化，一个紧凑的模型，这是一个组合的数学方程和提取的参数从BSIM 4，已开发的Verilog-A和编译到Cadence Virtuoso环境。该模型预测的迁移率变化和阈值电压在压缩和拉伸弯曲应力条件和取向，并显示与实验测量（1%的压缩和0.6%的拉伸应力失配）的协议。
The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18- $mu ext{m}$ technology were fabricated in two separated chips. The two fabricated chips were thinned down to $20~mu ext{m}$ using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch).
影响因子：
4.3
作者：
Heidari, Hadi;Bonizzoni, Edoardo;Dahiya, Ravinder
通讯作者：
Dahiya, Ravinder