An Energy-Efficient Network-on-Chip Design using Reinforcement Learning

An Energy-Efficient Network-on-Chip Design using Reinforcement Learning
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使用强化学习的节能片上网络设计

DOI:
10.1145/3316781.3317768
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发表时间:
2019
期刊:
56th ACM/IEEE Design Automation Conference (DAC
影响因子:
--
通讯作者:
Louri, Ahmed
Louri, Ahmed
中科院分区:
--
文献类型:
--
作者:
Zheng, Hao;Louri, Ahmed

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相似文献

节能片上网络(NoC)的设计空间已经显著扩展,包括许多技术。同时应用这些技术以产生最大的能量效率需要监测大量的系统参数,这通常导致大量的工程努力和复杂的控制策略。这促使我们探索使用强化学习(RL)方法,自动学习最优控制策略,以提高NoC的能源效率。首先,我们部署功率门控(PG)和动态电压和频率缩放(DVFS),同时降低静态和动态功耗。其次,我们使用RL自动探索PG,DVFS和系统参数之间的动态交互,学习路由器和缓存中包含的关键系统参数,并最终发展出最佳的每路由器控制策略,显着提高能源效率。此外,我们引入了一个人工神经网络(ANN),有效地实现RL所需的大型状态动作表。使用PARSEC基准测试的仿真结果表明,所提出的RL方法提高了26%的功耗,同时提高了7%的系统性能,相比没有RL的PG和DVFS的组合设计。此外,人工神经网络设计产生67%的面积减少,相比传统的RL实现。
The design space for energy-efficient Network-on-Chips (NoCs) has expanded significantly comprising a number of techniques. The simultaneous application of these techniques to yield maximum energy efficiency requires the monitoring of a large number of system parameters which often results in substantial engineering efforts and complicated control policies. This motivates us to explore the use of reinforcement learning (RL) approach that automatically learns an optimal control policy to improve NoC energy efficiency. First, we deploy power-gating (PG) and dynamic voltage and frequency scaling (DVFS) to simultaneously reduce both static and dynamic power. Second, we use RL to automatically explore the dynamic interactions among PG, DVFS, and system parameters, learn the critical system parameters contained in the router and cache, and eventually evolve optimal per-router control policies that significantly improve energy efficiency. Moreover, we introduce an artificial neural network (ANN) to efficiently implement the large state-action table required by RL. Simulation results using PARSEC benchmark show that the proposed RL approach improves power consumption by 26%, while improving system performance by 7%, as compared to a combined PG and DVFS design without RL. Additionally, the ANN design yields 67% area reduction, as compared to a conventional RL implementation.
DOI: 10.23919/date.2019.8714869
发表时间: 2019-03
期刊: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
影响因子: --
作者:
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DOI: --
发表时间: 2018
期刊:
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DOI: --
发表时间: 2020
期刊: Catalysis from A to Z
影响因子: --
作者:
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通过相干预测改进 NoC 中的 DVFS
DOI: 10.1145/2786572.2786595
发表时间: 2015
期刊: Proceedings of the 9th International Symposium on Networks-on-Chip
影响因子: --
作者:
R. Hesse;Natalie D. Enright Jerger
通讯作者: Natalie D. Enright Jerger