Routing Congestion Aware Cell Library Development for Monolithic 3D ICs
Routing Congestion Aware Cell Library Development for Monolithic 3D ICs
复制标题
单片 3D IC 的路由拥塞感知单元库开发
DOI：
10.1109/icrc.2017.8123686
复制
发表时间：
2017
期刊：
影响因子：
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通讯作者：
E. Salman
中科院分区：
文献类型：
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作者：
Chen Yan;E. Salman
根据国际设备和系统路线图（IRDS），2024年之后，没有用于2D几何缩放的空间。到2024年，IRDS预测，整体3D整合技术将成为最关键的性能促进者之一。该预测遵循了在单个底物上二线设备制造的高度前景和相对较新的改进。在这项研究中，开发了一个功能齐全的开源细胞库来设计和表征大规模整体式3D IC。第二版的3D单元库配备了所需的文件以集成到现有的设计自动化工具中，从而实现了芯片级的基准测试。此外，提出了多个库的版本，以调查路线，时机，权力和区域特征之间的权衡。 3D库还可以用于分析单片3D IC中的一些重要问题，例如芯片级的热特性，各种热管理方法的功效以及单片3D整合的设计方法。
According to International Roadmap for Devices and Systems (IRDS), after 2024, there is no headroom for 2D geometry scaling. By 2024, IRDS predicts that monolithic 3D integration technology will be one of the most critical performance boosters. This prediction follows the highly promising and relatively recent improvements on the fabrication of second-tier devices on a single substrate. In this study, a fully functional and open source cell library is developed to design and characterize large-scale monolithic 3D ICs. The second version of the 3D cell library is equipped with the required files for integration into existing design automation tools, thereby enabling chip-level benchmarking. Furthermore, multiple versions of the library are proposed to investigate the tradeoffs among routability, timing, power, and area characteristics. The 3D library can also be used to analyze some of the important issues in monolithic 3D ICs, such as chip-level thermal characteristics, efficacy of various thermal management methodologies, and design-for-test methods for monolithic 3D integration.
DOI：
10.1109/tcsii.2017.2749523
发表时间：
2018-06
期刊：
IEEE Transactions on Circuits and Systems II: Express Briefs
影响因子：
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作者：
Chen Yan;Jaya Dofe;Scott Kontak;Qiaoyan Yu;E. Salman
通讯作者：
Chen Yan;Jaya Dofe;Scott Kontak;Qiaoyan Yu;E. Salman