Characterisation and Modelling of Bulk CMOS Transistors over the 5 – 300 K Temperature Range
Characterisation and Modelling of Bulk CMOS Transistors over the 5 – 300 K Temperature Range
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5 – 300 K 温度范围内 Bulk CMOS 晶体管的表征和建模
DOI：
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
N. Dao
中科院分区：
文献类型：
--
作者：
N. Dao
随着MOSFET器件在极冷环境中工作的兴趣越来越大，低温应用的电路设计最近引起了人们的关注。器件表征和建模是电路设计中的关键步骤，需要在低温下进行晶体管表征的适当方法，以深入了解晶体管的行为，并在所需的工作温度下开发可靠的电路仿真模型。这项工作提出了一个详细的研究体CMOS晶体管的行为从室温下到5 K。提出了一种在宽温度范围内提取体CMOS器件内、外参数的新方法。提取的MOSFET参数揭示了在所研究的温度变化的特性。晶体管特性的基础上建立的设备和经验结果的物理特性。我们提出了一个增强的MOSFET阈值模型，基于一个简化的费米势和场辅助电离，来自物理和实验数据。我们的模型预测的阈值电压比传统的模型，特别是在低温下。一个自适应的载流子迁移率模型来自一个传统的模型进行了实验验证。我们开发了一个Verilog-A SPICE模型的基础上，我们的模型和提取结果。SPICE模型可以集成到Cadence Spectre仿真器中，用于低温下的电路仿真。我们的SPICE模型可以在很宽的温度范围内复制体CMOS的I-V特性。晶体管的匹配是高性能集成电路设计的一个重要方面。我们揭示，第一次，在5-300 K的温度范围内的MOSFET及其参数的匹配特性。提出了一个新的基于阈值电压、迁移率和串联电阻的体CMOS器件电流匹配计算公式。与现有公式相比，所提出的公式在低温下获得了更好的v结果。器件几何效应对MOSFET参数匹配和电流匹配的影响也被揭示出来。PMOS和NMOS器件的匹配结果提供了从室温到5 K的器件参数变化的视图。
With the increasing interest in MOSFET device operation in extremely cold environments, circuit designs for low temperature applications have attracted recent attention. Device characterisation and modelling are crucial steps in circuit designs, and an appropriate approach for transistor characterisation at cryogenic temperatures is required to provide insight into transistor behaviour, and to develop reliable models for circuit simulations over the required operating temperatures. This work presents a detailed study of bulk CMOS transistors behaviour from room temperature down to 5 K. A new approach to extract intrinsic and extrinsic parameters of bulk CMOS over a wide range of temperature is proposed. Extracted MOSFET parameters reveal changing characteristics over the examined temperatures. Transistor characteristics are modelled based on physical properties of device and empirical results. We proposed an enhanced MOSFET threshold model, based on a simplified Fermi potential and a field-assisted ionisation, derived from physics and experimental data. Our model predicts the threshold voltage better than the conventional model, especially at low temperatures. An adapted carrier mobility model derived from a conventional model is experimentally verified. We developed a Verilog-A SPICE model based on our model and extraction results. The SPICE model can be incorporated into Cadence Spectre simulator for circuit simulations at low temperatures. Our SPICE model can replicate the I-V characteristics of the bulk CMOS over a wide temperature range. The matching of transistors is one of the most important aspects of high performance integrated circuit design. We reveal, for the first time, the matching properties of MOSFETs and its parameters over the 5-300 K temperature range. We introduce a new formula to calculate the current matching in bulk CMOS devices based on the threshold voltage, mobility and series resistance. The proposed formula obtained better v results compared to the existing formula at low temperatures. The effects of device geometry effects on MOSFET parameter matching and current matching is also exposed. Matching results from PMOS and NMOS devices provide a view of device parameter variations from room temperature down to 5 K.
由于源极和漏极扩展中的随机掺杂波动导致完全耗尽型 SOI MOSFET 的统计变化
影响因子：
4.9
作者：
Markov S
通讯作者：
Markov S